[people/ms/u-boot.git] / arch / arm / include / asm / arch-tegra20 / display.h

/*
 *  (C) Copyright 2010
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
#define __ASM_ARCH_TEGRA_DISPLAY_H

#include <asm/arch-tegra/dc.h>
#include <fdtdec.h>
#include <asm/gpio.h>

/* This holds information about a window which can be displayed */
struct disp_ctl_win {
	enum win_color_depth_id fmt;	/* Color depth/format */
	unsigned	bpp;		/* Bits per pixel */
	phys_addr_t	phys_addr;	/* Physical address in memory */
	unsigned	x;		/* Horizontal address offset (bytes) */
	unsigned	y;		/* Veritical address offset (bytes) */
	unsigned	w;		/* Width of source window */
	unsigned	h;		/* Height of source window */
	unsigned	stride;		/* Number of bytes per line */
	unsigned	out_x;		/* Left edge of output window (col) */
	unsigned	out_y;		/* Top edge of output window (row) */
	unsigned	out_w;		/* Width of output window in pixels */
	unsigned	out_h;		/* Height of output window in pixels */
};

#define FDT_LCD_TIMINGS	4

enum {
	FDT_LCD_TIMING_REF_TO_SYNC,
	FDT_LCD_TIMING_SYNC_WIDTH,
	FDT_LCD_TIMING_BACK_PORCH,
	FDT_LCD_TIMING_FRONT_PORCH,

	FDT_LCD_TIMING_COUNT,
};

enum lcd_cache_t {
	FDT_LCD_CACHE_OFF		= 0,
	FDT_LCD_CACHE_WRITE_THROUGH	= 1 << 0,
	FDT_LCD_CACHE_WRITE_BACK	= 1 << 1,
	FDT_LCD_CACHE_FLUSH		= 1 << 2,
	FDT_LCD_CACHE_WRITE_BACK_FLUSH	= FDT_LCD_CACHE_WRITE_BACK |
						FDT_LCD_CACHE_FLUSH,
};

/* Information about the display controller */
struct fdt_disp_config {
	int valid;			/* config is valid */
	int width;			/* width in pixels */
	int height;			/* height in pixels */
	int bpp;			/* number of bits per pixel */

	/*
	 * log2 of number of bpp, in general, unless it bpp is 24 in which
	 * case this field holds 24 also! This is a U-Boot thing.
	 */
	int log2_bpp;
	struct disp_ctlr *disp;		/* Display controller to use */
	fdt_addr_t frame_buffer;	/* Address of frame buffer */
	unsigned pixel_clock;		/* Pixel clock in Hz */
	uint horiz_timing[FDT_LCD_TIMING_COUNT];	/* Horizontal timing */
	uint vert_timing[FDT_LCD_TIMING_COUNT];		/* Vertical timing */
	int panel_node;			/* node offset of panel information */
};

/* Information about the LCD panel */
struct fdt_panel_config {
	int pwm_channel;		/* PWM channel to use for backlight */
	enum lcd_cache_t cache_type;

	struct gpio_desc backlight_en;	/* GPIO for backlight enable */
	struct gpio_desc lvds_shutdown;	/* GPIO for lvds shutdown */
	struct gpio_desc backlight_vdd;	/* GPIO for backlight vdd */
	struct gpio_desc panel_vdd;	/* GPIO for panel vdd */
	/*
	 * Panel required timings
	 * Timing 1: delay between panel_vdd-rise and data-rise
	 * Timing 2: delay between data-rise and backlight_vdd-rise
	 * Timing 3: delay between backlight_vdd and pwm-rise
	 * Timing 4: delay between pwm-rise and backlight_en-rise
	 */
	uint panel_timings[FDT_LCD_TIMINGS];
};

/**
 * Perform the next stage of the LCD init if it is time to do so.
 *
 * LCD init can be time-consuming because of the number of delays we need
 * while waiting for the backlight power supply, etc. This function can
 * be called at various times during U-Boot operation to advance the
 * initialization of the LCD to the next stage if sufficient time has
 * passed since the last stage. It keeps track of what stage it is up to
 * and the time that it is permitted to move to the next stage.
 *
 * The final call should have wait=1 to complete the init.
 *
 * @param blob	fdt blob containing LCD information
 * @param wait	1 to wait until all init is complete, and then return
 *		0 to return immediately, potentially doing nothing if it is
 *		not yet time for the next init.
 */
int tegra_lcd_check_next_stage(const void *blob, int wait);

/**
 * Set up the maximum LCD size so we can size the frame buffer.
 *
 * @param blob	fdt blob containing LCD information
 */
void tegra_lcd_early_init(const void *blob);

#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
Commit	Line	Data
87540de3 WN	1	/*
	2	* (C) Copyright 2010
	3	* NVIDIA Corporation <www.nvidia.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
87540de3 WN	6	*/
	7
	8	#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
	9	#define __ASM_ARCH_TEGRA_DISPLAY_H
	10
2eb70de6	11	#include <asm/arch-tegra/dc.h>
87540de3	12	#include <fdtdec.h>
04072cba	13	#include <asm/gpio.h>
87540de3 WN	14
	15	/* This holds information about a window which can be displayed */
	16	struct disp_ctl_win {
	17	enum win_color_depth_id fmt; /* Color depth/format */
	18	unsigned bpp; /* Bits per pixel */
	19	phys_addr_t phys_addr; /* Physical address in memory */
	20	unsigned x; /* Horizontal address offset (bytes) */
	21	unsigned y; /* Veritical address offset (bytes) */
	22	unsigned w; /* Width of source window */
	23	unsigned h; /* Height of source window */
	24	unsigned stride; /* Number of bytes per line */
	25	unsigned out_x; /* Left edge of output window (col) */
	26	unsigned out_y; /* Top edge of output window (row) */
	27	unsigned out_w; /* Width of output window in pixels */
	28	unsigned out_h; /* Height of output window in pixels */
	29	};
	30
	31	#define FDT_LCD_TIMINGS 4
	32
	33	enum {
	34	FDT_LCD_TIMING_REF_TO_SYNC,
	35	FDT_LCD_TIMING_SYNC_WIDTH,
	36	FDT_LCD_TIMING_BACK_PORCH,
	37	FDT_LCD_TIMING_FRONT_PORCH,
	38
	39	FDT_LCD_TIMING_COUNT,
	40	};
	41
	42	enum lcd_cache_t {
	43	FDT_LCD_CACHE_OFF = 0,
	44	FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
	45	FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
	46	FDT_LCD_CACHE_FLUSH = 1 << 2,
	47	FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK \|
	48	FDT_LCD_CACHE_FLUSH,
	49	};
	50
	51	/* Information about the display controller */
	52	struct fdt_disp_config {
	53	int valid; /* config is valid */
	54	int width; /* width in pixels */
	55	int height; /* height in pixels */
	56	int bpp; /* number of bits per pixel */
	57
	58	/*
	59	* log2 of number of bpp, in general, unless it bpp is 24 in which
	60	* case this field holds 24 also! This is a U-Boot thing.
	61	*/
	62	int log2_bpp;
	63	struct disp_ctlr disp; / Display controller to use */
	64	fdt_addr_t frame_buffer; /* Address of frame buffer */
	65	unsigned pixel_clock; /* Pixel clock in Hz */
	66	uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
	67	uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
	68	int panel_node; /* node offset of panel information */
	69	};
	70
	71	/* Information about the LCD panel */
	72	struct fdt_panel_config {
	73	int pwm_channel; /* PWM channel to use for backlight */
	74	enum lcd_cache_t cache_type;
	75
04072cba SG	76	struct gpio_desc backlight_en; /* GPIO for backlight enable */
	77	struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
	78	struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
	79	struct gpio_desc panel_vdd; /* GPIO for panel vdd */
87540de3 WN	80	/*
	81	* Panel required timings
	82	* Timing 1: delay between panel_vdd-rise and data-rise
	83	* Timing 2: delay between data-rise and backlight_vdd-rise
	84	* Timing 3: delay between backlight_vdd and pwm-rise
	85	* Timing 4: delay between pwm-rise and backlight_en-rise
	86	*/
	87	uint panel_timings[FDT_LCD_TIMINGS];
	88	};
	89
87540de3 WN	90	/**
	91	* Perform the next stage of the LCD init if it is time to do so.
	92	*
	93	* LCD init can be time-consuming because of the number of delays we need
	94	* while waiting for the backlight power supply, etc. This function can
	95	* be called at various times during U-Boot operation to advance the
	96	* initialization of the LCD to the next stage if sufficient time has
	97	* passed since the last stage. It keeps track of what stage it is up to
	98	* and the time that it is permitted to move to the next stage.
	99	*
	100	* The final call should have wait=1 to complete the init.
	101	*
	102	* @param blob fdt blob containing LCD information
	103	* @param wait 1 to wait until all init is complete, and then return
	104	* 0 to return immediately, potentially doing nothing if it is
	105	* not yet time for the next init.
	106	*/
	107	int tegra_lcd_check_next_stage(const void *blob, int wait);
	108
	109	/**
	110	* Set up the maximum LCD size so we can size the frame buffer.
	111	*
	112	* @param blob fdt blob containing LCD information
	113	*/
	114	void tegra_lcd_early_init(const void *blob);
	115
	116	#endif /__ASM_ARCH_TEGRA_DISPLAY_H/