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84c7204b MS |
1 | /* |
2 | * (C) Copyright 2014 - 2015 Xilinx, Inc. | |
3 | * Michal Simek <michal.simek@xilinx.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef _ASM_ARCH_HARDWARE_H | |
9 | #define _ASM_ARCH_HARDWARE_H | |
10 | ||
cb7ea820 MS |
11 | #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 |
12 | #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 | |
13 | #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 | |
14 | #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 | |
15 | ||
2594e03c SDPP |
16 | #define ZYNQ_I2C_BASEADDR0 0xFF020000 |
17 | #define ZYNQ_I2C_BASEADDR1 0xFF030000 | |
18 | ||
78cb965a SDPP |
19 | #define ARASAN_NAND_BASEADDR 0xFF100000 |
20 | ||
16fa00a7 SDPP |
21 | #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 |
22 | #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 | |
23 | ||
e042d36e SDPP |
24 | #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 |
25 | #define ZYNQMP_TCM_SIZE 0x40000 | |
26 | ||
84c7204b MS |
27 | #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 |
28 | #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 | |
48255f52 MS |
29 | #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 |
30 | #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 | |
31 | ||
32 | #define PS_MODE0 BIT(0) | |
33 | #define PS_MODE1 BIT(1) | |
34 | #define PS_MODE2 BIT(2) | |
35 | #define PS_MODE3 BIT(3) | |
84c7204b MS |
36 | |
37 | struct crlapb_regs { | |
5cb24200 MS |
38 | u32 reserved0[36]; |
39 | u32 cpu_r5_ctrl; /* 0x90 */ | |
40 | u32 reserved1[37]; | |
84c7204b | 41 | u32 timestamp_ref_ctrl; /* 0x128 */ |
5cb24200 | 42 | u32 reserved2[53]; |
84c7204b | 43 | u32 boot_mode; /* 0x200 */ |
5cb24200 MS |
44 | u32 reserved3[14]; |
45 | u32 rst_lpd_top; /* 0x23C */ | |
48255f52 MS |
46 | u32 reserved4[4]; |
47 | u32 boot_pin_ctrl; /* 0x250 */ | |
48 | u32 reserved5[21]; | |
84c7204b MS |
49 | }; |
50 | ||
51 | #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) | |
52 | ||
0785dfd8 | 53 | #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 |
84c7204b MS |
54 | #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 |
55 | #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 | |
56 | ||
0785dfd8 MS |
57 | struct iou_scntr_secure { |
58 | u32 counter_control_register; | |
59 | u32 reserved0[7]; | |
60 | u32 base_frequency_id_register; | |
61 | }; | |
62 | ||
63 | #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) | |
64 | ||
84c7204b MS |
65 | /* Bootmode setting values */ |
66 | #define BOOT_MODES_MASK 0x0000000F | |
0a5bcc8c SDPP |
67 | #define QSPI_MODE_24BIT 0x00000001 |
68 | #define QSPI_MODE_32BIT 0x00000002 | |
af813acd MS |
69 | #define SD_MODE 0x00000003 /* sd 0 */ |
70 | #define SD_MODE1 0x00000005 /* sd 1 */ | |
0a5bcc8c | 71 | #define NAND_MODE 0x00000004 |
39c56f55 | 72 | #define EMMC_MODE 0x00000006 |
3373a522 | 73 | #define USB_MODE 0x00000007 |
e1992276 | 74 | #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ |
84c7204b | 75 | #define JTAG_MODE 0x00000000 |
7f491d7b MS |
76 | #define BOOT_MODE_USE_ALT 0x100 |
77 | #define BOOT_MODE_ALT_SHIFT 12 | |
2661081c MS |
78 | /* SW secondary boot modes 0xa - 0xd */ |
79 | #define SW_USBHOST_MODE 0x0000000A | |
80 | #define SW_SATA_MODE 0x0000000B | |
84c7204b | 81 | |
225bf9aa MS |
82 | #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 |
83 | ||
84 | struct iou_slcr_regs { | |
85 | u32 mio_pin[78]; | |
86 | u32 reserved[442]; | |
87 | }; | |
88 | ||
89 | #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) | |
90 | ||
5cb24200 MS |
91 | #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 |
92 | ||
93 | struct rpu_regs { | |
94 | u32 rpu_glbl_ctrl; | |
95 | u32 reserved0[63]; | |
96 | u32 rpu0_cfg; /* 0x100 */ | |
97 | u32 reserved1[63]; | |
98 | u32 rpu1_cfg; /* 0x200 */ | |
99 | }; | |
100 | ||
101 | #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) | |
102 | ||
103 | #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 | |
104 | ||
105 | struct crfapb_regs { | |
106 | u32 reserved0[65]; | |
107 | u32 rst_fpd_apu; /* 0x104 */ | |
108 | u32 reserved1; | |
109 | }; | |
110 | ||
111 | #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) | |
112 | ||
113 | #define ZYNQMP_APU_BASEADDR 0xFD5C0000 | |
114 | ||
115 | struct apu_regs { | |
116 | u32 reserved0[16]; | |
117 | u32 rvbar_addr0_l; /* 0x40 */ | |
118 | u32 rvbar_addr0_h; /* 0x44 */ | |
119 | u32 reserved1[20]; | |
120 | }; | |
121 | ||
122 | #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) | |
123 | ||
84c7204b | 124 | /* Board version value */ |
0785dfd8 | 125 | #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 |
84c7204b MS |
126 | #define ZYNQMP_CSU_VERSION_SILICON 0x0 |
127 | #define ZYNQMP_CSU_VERSION_EP108 0x1 | |
16247d28 | 128 | #define ZYNQMP_CSU_VERSION_VELOCE 0x2 |
84c7204b MS |
129 | #define ZYNQMP_CSU_VERSION_QEMU 0x3 |
130 | ||
494fffe7 MS |
131 | #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 |
132 | ||
0785dfd8 MS |
133 | #define ZYNQMP_SILICON_VER_MASK 0xF000 |
134 | #define ZYNQMP_SILICON_VER_SHIFT 12 | |
135 | ||
136 | struct csu_regs { | |
137 | u32 reserved0[17]; | |
138 | u32 version; | |
139 | }; | |
140 | ||
141 | #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) | |
142 | ||
509d4b95 MS |
143 | #define ZYNQMP_PMU_BASEADDR 0xFFD80000 |
144 | ||
145 | struct pmu_regs { | |
146 | u32 reserved[18]; | |
147 | u32 gen_storage6; /* 0x48 */ | |
148 | }; | |
149 | ||
150 | #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) | |
151 | ||
74ba69db SDPP |
152 | #define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 |
153 | #define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 | |
154 | ||
84c7204b | 155 | #endif /* _ASM_ARCH_HARDWARE_H */ |