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84c7204b MS |
1 | /* |
2 | * (C) Copyright 2014 - 2015 Xilinx, Inc. | |
3 | * Michal Simek <michal.simek@xilinx.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef _ASM_ARCH_HARDWARE_H | |
9 | #define _ASM_ARCH_HARDWARE_H | |
10 | ||
cb7ea820 MS |
11 | #define ZYNQ_GEM_BASEADDR0 0xFF0B0000 |
12 | #define ZYNQ_GEM_BASEADDR1 0xFF0C0000 | |
13 | #define ZYNQ_GEM_BASEADDR2 0xFF0D0000 | |
14 | #define ZYNQ_GEM_BASEADDR3 0xFF0E0000 | |
15 | ||
48d7260d SDPP |
16 | #define ZYNQ_SPI_BASEADDR0 0xFF040000 |
17 | #define ZYNQ_SPI_BASEADDR1 0xFF050000 | |
18 | ||
2594e03c SDPP |
19 | #define ZYNQ_I2C_BASEADDR0 0xFF020000 |
20 | #define ZYNQ_I2C_BASEADDR1 0xFF030000 | |
21 | ||
78cb965a SDPP |
22 | #define ARASAN_NAND_BASEADDR 0xFF100000 |
23 | ||
6fe6f135 MS |
24 | #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 |
25 | ||
16fa00a7 SDPP |
26 | #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 |
27 | #define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000 | |
28 | ||
84c7204b MS |
29 | #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 |
30 | #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 | |
31 | ||
32 | struct crlapb_regs { | |
5cb24200 MS |
33 | u32 reserved0[36]; |
34 | u32 cpu_r5_ctrl; /* 0x90 */ | |
35 | u32 reserved1[37]; | |
84c7204b | 36 | u32 timestamp_ref_ctrl; /* 0x128 */ |
5cb24200 | 37 | u32 reserved2[53]; |
84c7204b | 38 | u32 boot_mode; /* 0x200 */ |
5cb24200 MS |
39 | u32 reserved3[14]; |
40 | u32 rst_lpd_top; /* 0x23C */ | |
41 | u32 reserved4[26]; | |
84c7204b MS |
42 | }; |
43 | ||
44 | #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) | |
45 | ||
0785dfd8 | 46 | #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 |
84c7204b MS |
47 | #define ZYNQMP_IOU_SCNTR 0xFF250000 |
48 | #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 | |
49 | #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 | |
50 | ||
51 | struct iou_scntr { | |
52 | u32 counter_control_register; | |
53 | u32 reserved0[7]; | |
54 | u32 base_frequency_id_register; | |
55 | }; | |
56 | ||
57 | #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) | |
58 | ||
0785dfd8 MS |
59 | struct iou_scntr_secure { |
60 | u32 counter_control_register; | |
61 | u32 reserved0[7]; | |
62 | u32 base_frequency_id_register; | |
63 | }; | |
64 | ||
65 | #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) | |
66 | ||
84c7204b MS |
67 | /* Bootmode setting values */ |
68 | #define BOOT_MODES_MASK 0x0000000F | |
0a5bcc8c SDPP |
69 | #define QSPI_MODE_24BIT 0x00000001 |
70 | #define QSPI_MODE_32BIT 0x00000002 | |
af813acd MS |
71 | #define SD_MODE 0x00000003 /* sd 0 */ |
72 | #define SD_MODE1 0x00000005 /* sd 1 */ | |
0a5bcc8c | 73 | #define NAND_MODE 0x00000004 |
39c56f55 | 74 | #define EMMC_MODE 0x00000006 |
84c7204b MS |
75 | #define JTAG_MODE 0x00000000 |
76 | ||
225bf9aa MS |
77 | #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 |
78 | ||
79 | struct iou_slcr_regs { | |
80 | u32 mio_pin[78]; | |
81 | u32 reserved[442]; | |
82 | }; | |
83 | ||
84 | #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) | |
85 | ||
5cb24200 MS |
86 | #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 |
87 | ||
88 | struct rpu_regs { | |
89 | u32 rpu_glbl_ctrl; | |
90 | u32 reserved0[63]; | |
91 | u32 rpu0_cfg; /* 0x100 */ | |
92 | u32 reserved1[63]; | |
93 | u32 rpu1_cfg; /* 0x200 */ | |
94 | }; | |
95 | ||
96 | #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) | |
97 | ||
98 | #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 | |
99 | ||
100 | struct crfapb_regs { | |
101 | u32 reserved0[65]; | |
102 | u32 rst_fpd_apu; /* 0x104 */ | |
103 | u32 reserved1; | |
104 | }; | |
105 | ||
106 | #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) | |
107 | ||
108 | #define ZYNQMP_APU_BASEADDR 0xFD5C0000 | |
109 | ||
110 | struct apu_regs { | |
111 | u32 reserved0[16]; | |
112 | u32 rvbar_addr0_l; /* 0x40 */ | |
113 | u32 rvbar_addr0_h; /* 0x44 */ | |
114 | u32 reserved1[20]; | |
115 | }; | |
116 | ||
117 | #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) | |
118 | ||
84c7204b | 119 | /* Board version value */ |
0785dfd8 | 120 | #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 |
84c7204b MS |
121 | #define ZYNQMP_CSU_VERSION_SILICON 0x0 |
122 | #define ZYNQMP_CSU_VERSION_EP108 0x1 | |
16247d28 | 123 | #define ZYNQMP_CSU_VERSION_VELOCE 0x2 |
84c7204b MS |
124 | #define ZYNQMP_CSU_VERSION_QEMU 0x3 |
125 | ||
0785dfd8 MS |
126 | #define ZYNQMP_SILICON_VER_MASK 0xF000 |
127 | #define ZYNQMP_SILICON_VER_SHIFT 12 | |
128 | ||
129 | struct csu_regs { | |
130 | u32 reserved0[17]; | |
131 | u32 version; | |
132 | }; | |
133 | ||
134 | #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) | |
135 | ||
84c7204b | 136 | #endif /* _ASM_ARCH_HARDWARE_H */ |