projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 2c451f78 A |
1 | /* |
| 2 | * (C) Copyright 2010 | |
| 3 | * Texas Instruments, <www.ti.com> | |
| 4 | * Aneesh V <aneesh@ti.com> | |
| 5 | * | |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 2c451f78 A |
7 | */ |
| 8 | #ifndef ARMV7_H | |
| 9 | #define ARMV7_H | |
| 10 | #include <linux/types.h> | |
| 11 | ||
| ad577c8a A |
12 | /* Cortex-A9 revisions */ |
| 13 | #define MIDR_CORTEX_A9_R0P1 0x410FC091 | |
| 14 | #define MIDR_CORTEX_A9_R1P2 0x411FC092 | |
| 15 | #define MIDR_CORTEX_A9_R1P3 0x411FC093 | |
| 5ab12a9e | 16 | #define MIDR_CORTEX_A9_R2P10 0x412FC09A |
| ad577c8a | 17 | |
| 508a58fa S |
18 | /* Cortex-A15 revisions */ |
| 19 | #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 | |
| eed7c0f7 | 20 | #define MIDR_CORTEX_A15_R2P2 0x412FC0F2 |
| 508a58fa | 21 | |
| 2c451f78 A |
22 | /* CCSIDR */ |
| 23 | #define CCSIDR_LINE_SIZE_OFFSET 0 | |
| 24 | #define CCSIDR_LINE_SIZE_MASK 0x7 | |
| 25 | #define CCSIDR_ASSOCIATIVITY_OFFSET 3 | |
| 26 | #define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3) | |
| 27 | #define CCSIDR_NUM_SETS_OFFSET 13 | |
| 28 | #define CCSIDR_NUM_SETS_MASK (0x7FFF << 13) | |
| 29 | ||
| 30 | /* | |
| 31 | * Values for InD field in CSSELR | |
| 32 | * Selects the type of cache | |
| 33 | */ | |
| 34 | #define ARMV7_CSSELR_IND_DATA_UNIFIED 0 | |
| 35 | #define ARMV7_CSSELR_IND_INSTRUCTION 1 | |
| 36 | ||
| 37 | /* Values for Ctype fields in CLIDR */ | |
| 38 | #define ARMV7_CLIDR_CTYPE_NO_CACHE 0 | |
| 39 | #define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1 | |
| 40 | #define ARMV7_CLIDR_CTYPE_DATA_ONLY 2 | |
| 41 | #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 | |
| 42 | #define ARMV7_CLIDR_CTYPE_UNIFIED 4 | |
| 43 | ||
| 44 | /* | |
| 45 | * CP15 Barrier instructions | |
| 46 | * Please note that we have separate barrier instructions in ARMv7 | |
| 47 | * However, we use the CP15 based instructtions because we use | |
| 48 | * -march=armv5 in U-Boot | |
| 49 | */ | |
| 50 | #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) | |
| 51 | #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) | |
| 52 | #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) | |
| 53 | ||
| 54 | void v7_outer_cache_enable(void); | |
| 55 | void v7_outer_cache_disable(void); | |
| 56 | void v7_outer_cache_flush_all(void); | |
| 57 | void v7_outer_cache_inval_all(void); | |
| 58 | void v7_outer_cache_flush_range(u32 start, u32 end); | |
| 59 | void v7_outer_cache_inval_range(u32 start, u32 end); | |
| 60 | ||
| 61 | #endif |