[people/ms/u-boot.git] / arch / arm / include / asm / armv8 / mmu.h

/*
 * (C) Copyright 2013
 * David Feng <fenghua@phytium.com.cn>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_

/***************************************************************/
/*
 * The following definitions are related each other, shoud be
 * calculated specifically.
 */

#define VA_BITS			CONFIG_SYS_VA_BITS
#define PTE_BLOCK_BITS		CONFIG_SYS_PTL2_BITS

/*
 * block/section address mask and size definitions.
 */

/* PAGE_SHIFT determines the page size */
#undef  PAGE_SIZE
#define PAGE_SHIFT		12
#define PAGE_SIZE		(1 << PAGE_SHIFT)
#define PAGE_MASK		(~(PAGE_SIZE-1))

/***************************************************************/

/*
 * Memory types
 */
#define MT_DEVICE_NGNRNE	0
#define MT_DEVICE_NGNRE		1
#define MT_DEVICE_GRE		2
#define MT_NORMAL_NC		3
#define MT_NORMAL		4

#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE * 8)) |	\
				(0x04 << (MT_DEVICE_NGNRE * 8))   |	\
				(0x0c << (MT_DEVICE_GRE * 8))     |	\
				(0x44 << (MT_NORMAL_NC * 8))      |	\
				(UL(0xff) << (MT_NORMAL * 8)))

/*
 * Hardware page table definitions.
 *
 */

#define PTE_TYPE_MASK		(3 << 0)
#define PTE_TYPE_FAULT		(0 << 0)
#define PTE_TYPE_TABLE		(3 << 0)
#define PTE_TYPE_BLOCK		(1 << 0)

#define PTE_TABLE_PXN		(1UL << 59)
#define PTE_TABLE_XN		(1UL << 60)
#define PTE_TABLE_AP		(1UL << 61)
#define PTE_TABLE_NS		(1UL << 63)

/*
 * Block
 */
#define PTE_BLOCK_MEMTYPE(x)	((x) << 2)
#define PTE_BLOCK_NS            (1 << 5)
#define PTE_BLOCK_NON_SHARE	(0 << 8)
#define PTE_BLOCK_OUTER_SHARE	(2 << 8)
#define PTE_BLOCK_INNER_SHARE	(3 << 8)
#define PTE_BLOCK_AF		(1 << 10)
#define PTE_BLOCK_NG		(1 << 11)
#define PTE_BLOCK_PXN		(UL(1) << 53)
#define PTE_BLOCK_UXN		(UL(1) << 54)

/*
 * AttrIndx[2:0]
 */
#define PMD_ATTRINDX(t)		((t) << 2)
#define PMD_ATTRINDX_MASK	(7 << 2)

/*
 * TCR flags.
 */
#define TCR_T0SZ(x)		((64 - (x)) << 0)
#define TCR_IRGN_NC		(0 << 8)
#define TCR_IRGN_WBWA		(1 << 8)
#define TCR_IRGN_WT		(2 << 8)
#define TCR_IRGN_WBNWA		(3 << 8)
#define TCR_IRGN_MASK		(3 << 8)
#define TCR_ORGN_NC		(0 << 10)
#define TCR_ORGN_WBWA		(1 << 10)
#define TCR_ORGN_WT		(2 << 10)
#define TCR_ORGN_WBNWA		(3 << 10)
#define TCR_ORGN_MASK		(3 << 10)
#define TCR_SHARED_NON		(0 << 12)
#define TCR_SHARED_OUTER	(2 << 12)
#define TCR_SHARED_INNER	(3 << 12)
#define TCR_TG0_4K		(0 << 14)
#define TCR_TG0_64K		(1 << 14)
#define TCR_TG0_16K		(2 << 14)
#define TCR_EPD1_DISABLE	(1 << 23)

#define TCR_EL1_RSVD		(1 << 31)
#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)

#ifndef __ASSEMBLY__
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
	asm volatile("dsb sy");
	if (el == 1) {
		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	} else if (el == 2) {
		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	} else if (el == 3) {
		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	} else {
		hang();
	}
	asm volatile("isb");
}

struct mm_region {
	u64 virt;
	u64 phys;
	u64 size;
	u64 attrs;
};

extern struct mm_region *mem_map;
void setup_pgtables(void);
u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
#endif

#endif /* _ASM_ARMV8_MMU_H_ */
Commit	Line	Data
0ae76531 DF	1	/*
	2	* (C) Copyright 2013
	3	* David Feng <fenghua@phytium.com.cn>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef _ASM_ARMV8_MMU_H_
	9	#define _ASM_ARMV8_MMU_H_
	10
0ae76531 DF	11	/***************************************************************/
	12	/*
	13	* The following definitions are related each other, shoud be
	14	* calculated specifically.
	15	*/
94f7ff36	16
94f7ff36	17	#define VA_BITS CONFIG_SYS_VA_BITS
5e2ec773	18	#define PTE_BLOCK_BITS CONFIG_SYS_PTL2_BITS
0ae76531	19
0ae76531	20	/*
94f7ff36	21	* block/section address mask and size definitions.
0ae76531	22	*/
5e2ec773 AG	23
	24	/* PAGE_SHIFT determines the page size */
	25	#undef PAGE_SIZE
	26	#define PAGE_SHIFT 12
	27	#define PAGE_SIZE (1 << PAGE_SHIFT)
	28	#define PAGE_MASK (~(PAGE_SIZE-1))
	29
0ae76531 DF	30	/***************************************************************/
	31
	32	/*
	33	* Memory types
	34	*/
	35	#define MT_DEVICE_NGNRNE 0
	36	#define MT_DEVICE_NGNRE 1
	37	#define MT_DEVICE_GRE 2
	38	#define MT_NORMAL_NC 3
	39	#define MT_NORMAL 4
	40
94f7ff36 ST	41	#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) \| \
	42	(0x04 << (MT_DEVICE_NGNRE * 8)) \| \
	43	(0x0c << (MT_DEVICE_GRE * 8)) \| \
	44	(0x44 << (MT_NORMAL_NC * 8)) \| \
	45	(UL(0xff) << (MT_NORMAL * 8)))
0ae76531 DF	46
	47	/*
	48	* Hardware page table definitions.
	49	*
94f7ff36 ST	50	*/
94f7ff36 ST	51
5e2ec773 AG	52	#define PTE_TYPE_MASK (3 << 0)
	53	#define PTE_TYPE_FAULT (0 << 0)
	54	#define PTE_TYPE_TABLE (3 << 0)
	55	#define PTE_TYPE_BLOCK (1 << 0)
94f7ff36	56
5e2ec773 AG	57	#define PTE_TABLE_PXN (1UL << 59)
	58	#define PTE_TABLE_XN (1UL << 60)
	59	#define PTE_TABLE_AP (1UL << 61)
	60	#define PTE_TABLE_NS (1UL << 63)
94f7ff36 ST	61
	62	/*
	63	* Block
	64	*/
5e2ec773	65	#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
7985cdf7	66	#define PTE_BLOCK_NS (1 << 5)
5e2ec773 AG	67	#define PTE_BLOCK_NON_SHARE (0 << 8)
	68	#define PTE_BLOCK_OUTER_SHARE (2 << 8)
	69	#define PTE_BLOCK_INNER_SHARE (3 << 8)
	70	#define PTE_BLOCK_AF (1 << 10)
	71	#define PTE_BLOCK_NG (1 << 11)
	72	#define PTE_BLOCK_PXN (UL(1) << 53)
	73	#define PTE_BLOCK_UXN (UL(1) << 54)
94f7ff36	74
0ae76531 DF	75	/*
	76	* AttrIndx[2:0]
	77	*/
	78	#define PMD_ATTRINDX(t) ((t) << 2)
	79	#define PMD_ATTRINDX_MASK (7 << 2)
	80
	81	/*
	82	* TCR flags.
	83	*/
	84	#define TCR_T0SZ(x) ((64 - (x)) << 0)
	85	#define TCR_IRGN_NC (0 << 8)
	86	#define TCR_IRGN_WBWA (1 << 8)
	87	#define TCR_IRGN_WT (2 << 8)
	88	#define TCR_IRGN_WBNWA (3 << 8)
	89	#define TCR_IRGN_MASK (3 << 8)
	90	#define TCR_ORGN_NC (0 << 10)
	91	#define TCR_ORGN_WBWA (1 << 10)
	92	#define TCR_ORGN_WT (2 << 10)
	93	#define TCR_ORGN_WBNWA (3 << 10)
	94	#define TCR_ORGN_MASK (3 << 10)
	95	#define TCR_SHARED_NON (0 << 12)
21a257b9 ZH	96	#define TCR_SHARED_OUTER (2 << 12)
21a257b9 ZH	97	#define TCR_SHARED_INNER (3 << 12)
0ae76531 DF	98	#define TCR_TG0_4K (0 << 14)
	99	#define TCR_TG0_64K (1 << 14)
	100	#define TCR_TG0_16K (2 << 14)
9bb367a5	101	#define TCR_EPD1_DISABLE (1 << 23)
94f7ff36	102
ad3d6e88 TR	103	#define TCR_EL1_RSVD (1 << 31)
	104	#define TCR_EL2_RSVD (1 << 31 \| 1 << 23)
	105	#define TCR_EL3_RSVD (1 << 31 \| 1 << 23)
	106
22932ffc	107	#ifndef __ASSEMBLY__
22932ffc YS	108	static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
	109	{
	110	asm volatile("dsb sy");
	111	if (el == 1) {
	112	asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
	113	asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
	114	asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	115	} else if (el == 2) {
	116	asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
	117	asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
	118	asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	119	} else if (el == 3) {
	120	asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
	121	asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
	122	asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	123	} else {
	124	hang();
	125	}
	126	asm volatile("isb");
	127	}
94f7ff36 ST	128
94f7ff36 ST	129	struct mm_region {
cd4b0c5f YS	130	u64 virt;
cd4b0c5f YS	131	u64 phys;
94f7ff36 ST	132	u64 size;
	133	u64 attrs;
	134	};
d473f0c6 AG	135
d473f0c6 AG	136	extern struct mm_region *mem_map;
252cdb46 YS	137	void setup_pgtables(void);
252cdb46 YS	138	u64 get_tcr(int el, u64 pips, u64 pva_bits);
22932ffc	139	#endif
94f7ff36	140
0ae76531	141	#endif /* _ASM_ARMV8_MMU_H_ */