[people/ms/u-boot.git] / arch / arm / include / asm / armv8 / mmu.h

/*
 * (C) Copyright 2013
 * David Feng <fenghua@phytium.com.cn>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_

#ifdef __ASSEMBLY__
#define _AC(X, Y)	X
#else
#define _AC(X, Y)	(X##Y)
#endif

#define UL(x)		_AC(x, UL)

/***************************************************************/
/*
 * The following definitions are related each other, shoud be
 * calculated specifically.
 */
#define VA_BITS			(42)	/* 42 bits virtual address */

/* PAGE_SHIFT determines the page size */
#undef  PAGE_SIZE
#define PAGE_SHIFT		16
#define PAGE_SIZE		(1 << PAGE_SHIFT)
#define PAGE_MASK		(~(PAGE_SIZE-1))

/*
 * section address mask and size definitions.
 */
#define SECTION_SHIFT		29
#define SECTION_SIZE		(UL(1) << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))
/***************************************************************/

/*
 * Memory types
 */
#define MT_DEVICE_NGNRNE	0
#define MT_DEVICE_NGNRE		1
#define MT_DEVICE_GRE		2
#define MT_NORMAL_NC		3
#define MT_NORMAL		4

#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE*8)) |	\
				(0x04 << (MT_DEVICE_NGNRE*8)) |		\
				(0x0c << (MT_DEVICE_GRE*8)) |		\
				(0x44 << (MT_NORMAL_NC*8)) |		\
				(UL(0xff) << (MT_NORMAL*8)))

/*
 * Hardware page table definitions.
 *
 * Level 2 descriptor (PMD).
 */
#define PMD_TYPE_MASK		(3 << 0)
#define PMD_TYPE_FAULT		(0 << 0)
#define PMD_TYPE_TABLE		(3 << 0)
#define PMD_TYPE_SECT		(1 << 0)

/*
 * Section
 */
#define PMD_SECT_NON_SHARE	(0 << 8)
#define PMD_SECT_OUTER_SHARE	(2 << 8)
#define PMD_SECT_INNER_SHARE	(3 << 8)
#define PMD_SECT_AF		(1 << 10)
#define PMD_SECT_NG		(1 << 11)
#define PMD_SECT_PXN		(UL(1) << 53)
#define PMD_SECT_UXN		(UL(1) << 54)

/*
 * AttrIndx[2:0]
 */
#define PMD_ATTRINDX(t)		((t) << 2)
#define PMD_ATTRINDX_MASK	(7 << 2)

/*
 * TCR flags.
 */
#define TCR_T0SZ(x)		((64 - (x)) << 0)
#define TCR_IRGN_NC		(0 << 8)
#define TCR_IRGN_WBWA		(1 << 8)
#define TCR_IRGN_WT		(2 << 8)
#define TCR_IRGN_WBNWA		(3 << 8)
#define TCR_IRGN_MASK		(3 << 8)
#define TCR_ORGN_NC		(0 << 10)
#define TCR_ORGN_WBWA		(1 << 10)
#define TCR_ORGN_WT		(2 << 10)
#define TCR_ORGN_WBNWA		(3 << 10)
#define TCR_ORGN_MASK		(3 << 10)
#define TCR_SHARED_NON		(0 << 12)
#define TCR_SHARED_OUTER	(2 << 12)
#define TCR_SHARED_INNER	(3 << 12)
#define TCR_TG0_4K		(0 << 14)
#define TCR_TG0_64K		(1 << 14)
#define TCR_TG0_16K		(2 << 14)
#define TCR_EL1_IPS_BITS	(UL(3) << 32)	/* 42 bits physical address */
#define TCR_EL2_IPS_BITS	(3 << 16)	/* 42 bits physical address */
#define TCR_EL3_IPS_BITS	(3 << 16)	/* 42 bits physical address */

/* PTWs cacheable, inner/outer WBWA and inner shareable */
#define TCR_FLAGS		(TCR_TG0_64K |		\
				TCR_SHARED_INNER |	\
				TCR_ORGN_WBWA |		\
				TCR_IRGN_WBWA |		\
				TCR_T0SZ(VA_BITS))

#define TCR_EL1_RSVD		(1 << 31)
#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)

#ifndef __ASSEMBLY__

void set_pgtable_section(u64 *page_table, u64 index,
			 u64 section, u64 memory_type,
			 u64 share);
void set_pgtable_table(u64 *page_table, u64 index,
		       u64 *table_addr);

static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
	asm volatile("dsb sy");
	if (el == 1) {
		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	} else if (el == 2) {
		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	} else if (el == 3) {
		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	} else {
		hang();
	}
	asm volatile("isb");
}
#endif
#endif /* _ASM_ARMV8_MMU_H_ */
Commit	Line	Data
0ae76531 DF	1	/*
	2	* (C) Copyright 2013
	3	* David Feng <fenghua@phytium.com.cn>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef _ASM_ARMV8_MMU_H_
	9	#define _ASM_ARMV8_MMU_H_
	10
	11	#ifdef __ASSEMBLY__
	12	#define _AC(X, Y) X
	13	#else
	14	#define _AC(X, Y) (X##Y)
	15	#endif
	16
	17	#define UL(x) _AC(x, UL)
	18
	19	/***************************************************************/
	20	/*
	21	* The following definitions are related each other, shoud be
	22	* calculated specifically.
	23	*/
	24	#define VA_BITS (42) /* 42 bits virtual address */
	25
	26	/* PAGE_SHIFT determines the page size */
	27	#undef PAGE_SIZE
	28	#define PAGE_SHIFT 16
	29	#define PAGE_SIZE (1 << PAGE_SHIFT)
	30	#define PAGE_MASK (~(PAGE_SIZE-1))
	31
	32	/*
	33	* section address mask and size definitions.
	34	*/
	35	#define SECTION_SHIFT 29
	36	#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
	37	#define SECTION_MASK (~(SECTION_SIZE-1))
	38	/***************************************************************/
	39
	40	/*
	41	* Memory types
	42	*/
	43	#define MT_DEVICE_NGNRNE 0
	44	#define MT_DEVICE_NGNRE 1
	45	#define MT_DEVICE_GRE 2
	46	#define MT_NORMAL_NC 3
	47	#define MT_NORMAL 4
	48
	49	#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) \| \
	50	(0x04 << (MT_DEVICE_NGNRE*8)) \| \
	51	(0x0c << (MT_DEVICE_GRE*8)) \| \
	52	(0x44 << (MT_NORMAL_NC*8)) \| \
	53	(UL(0xff) << (MT_NORMAL*8)))
	54
	55	/*
	56	* Hardware page table definitions.
	57	*
	58	* Level 2 descriptor (PMD).
	59	*/
	60	#define PMD_TYPE_MASK (3 << 0)
	61	#define PMD_TYPE_FAULT (0 << 0)
	62	#define PMD_TYPE_TABLE (3 << 0)
	63	#define PMD_TYPE_SECT (1 << 0)
	64
65	/*
66	* Section
67	*/
99799220	68	#define PMD_SECT_NON_SHARE (0 << 8)
6c747f4a YS	69	#define PMD_SECT_OUTER_SHARE (2 << 8)
6c747f4a YS	70	#define PMD_SECT_INNER_SHARE (3 << 8)
0ae76531 DF	71	#define PMD_SECT_AF (1 << 10)
	72	#define PMD_SECT_NG (1 << 11)
	73	#define PMD_SECT_PXN (UL(1) << 53)
	74	#define PMD_SECT_UXN (UL(1) << 54)
	75
	76	/*
	77	* AttrIndx[2:0]
	78	*/
	79	#define PMD_ATTRINDX(t) ((t) << 2)
	80	#define PMD_ATTRINDX_MASK (7 << 2)
	81
	82	/*
	83	* TCR flags.
	84	*/
	85	#define TCR_T0SZ(x) ((64 - (x)) << 0)
	86	#define TCR_IRGN_NC (0 << 8)
	87	#define TCR_IRGN_WBWA (1 << 8)
	88	#define TCR_IRGN_WT (2 << 8)
	89	#define TCR_IRGN_WBNWA (3 << 8)
	90	#define TCR_IRGN_MASK (3 << 8)
	91	#define TCR_ORGN_NC (0 << 10)
	92	#define TCR_ORGN_WBWA (1 << 10)
	93	#define TCR_ORGN_WT (2 << 10)
	94	#define TCR_ORGN_WBNWA (3 << 10)
	95	#define TCR_ORGN_MASK (3 << 10)
	96	#define TCR_SHARED_NON (0 << 12)
21a257b9 ZH	97	#define TCR_SHARED_OUTER (2 << 12)
21a257b9 ZH	98	#define TCR_SHARED_INNER (3 << 12)
0ae76531 DF	99	#define TCR_TG0_4K (0 << 14)
	100	#define TCR_TG0_64K (1 << 14)
	101	#define TCR_TG0_16K (2 << 14)
	102	#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
	103	#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
	104	#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
	105
55aa0bed	106	/* PTWs cacheable, inner/outer WBWA and inner shareable */
0ae76531	107	#define TCR_FLAGS (TCR_TG0_64K \| \
55aa0bed	108	TCR_SHARED_INNER \| \
0ae76531 DF	109	TCR_ORGN_WBWA \| \
	110	TCR_IRGN_WBWA \| \
	111	TCR_T0SZ(VA_BITS))
	112
ad3d6e88 TR	113	#define TCR_EL1_RSVD (1 << 31)
	114	#define TCR_EL2_RSVD (1 << 31 \| 1 << 23)
	115	#define TCR_EL3_RSVD (1 << 31 \| 1 << 23)
	116
22932ffc	117	#ifndef __ASSEMBLY__
99799220	118
22932ffc	119	void set_pgtable_section(u64 *page_table, u64 index,
99799220 AW	120	u64 section, u64 memory_type,
	121	u64 share);
	122	void set_pgtable_table(u64 *page_table, u64 index,
	123	u64 *table_addr);
	124
22932ffc YS	125	static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
	126	{
	127	asm volatile("dsb sy");
	128	if (el == 1) {
	129	asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
	130	asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
	131	asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	132	} else if (el == 2) {
	133	asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
	134	asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
	135	asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	136	} else if (el == 3) {
	137	asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
	138	asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
	139	asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	140	} else {
	141	hang();
	142	}
	143	asm volatile("isb");
	144	}
	145	#endif
0ae76531	146	#endif /* _ASM_ARMV8_MMU_H_ */