[people/ms/u-boot.git] / arch / arm / include / asm / armv8 / mmu.h

/*
 * (C) Copyright 2013
 * David Feng <fenghua@phytium.com.cn>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_

/*
 * block/section address mask and size definitions.
 */

/* PAGE_SHIFT determines the page size */
#undef  PAGE_SIZE
#define PAGE_SHIFT		12
#define PAGE_SIZE		(1 << PAGE_SHIFT)
#define PAGE_MASK		(~(PAGE_SIZE - 1))

/***************************************************************/

/*
 * Memory types
 */
#define MT_DEVICE_NGNRNE	0
#define MT_DEVICE_NGNRE		1
#define MT_DEVICE_GRE		2
#define MT_NORMAL_NC		3
#define MT_NORMAL		4

#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE * 8)) |	\
				(0x04 << (MT_DEVICE_NGNRE * 8))   |	\
				(0x0c << (MT_DEVICE_GRE * 8))     |	\
				(0x44 << (MT_NORMAL_NC * 8))      |	\
				(UL(0xff) << (MT_NORMAL * 8)))

/*
 * Hardware page table definitions.
 *
 */

#define PTE_TYPE_MASK		(3 << 0)
#define PTE_TYPE_FAULT		(0 << 0)
#define PTE_TYPE_TABLE		(3 << 0)
#define PTE_TYPE_PAGE		(3 << 0)
#define PTE_TYPE_BLOCK		(1 << 0)
#define PTE_TYPE_VALID		(1 << 0)

#define PTE_TABLE_PXN		(1UL << 59)
#define PTE_TABLE_XN		(1UL << 60)
#define PTE_TABLE_AP		(1UL << 61)
#define PTE_TABLE_NS		(1UL << 63)

/*
 * Block
 */
#define PTE_BLOCK_MEMTYPE(x)	((x) << 2)
#define PTE_BLOCK_NS            (1 << 5)
#define PTE_BLOCK_NON_SHARE	(0 << 8)
#define PTE_BLOCK_OUTER_SHARE	(2 << 8)
#define PTE_BLOCK_INNER_SHARE	(3 << 8)
#define PTE_BLOCK_AF		(1 << 10)
#define PTE_BLOCK_NG		(1 << 11)
#define PTE_BLOCK_PXN		(UL(1) << 53)
#define PTE_BLOCK_UXN		(UL(1) << 54)

/*
 * AttrIndx[2:0]
 */
#define PMD_ATTRINDX(t)		((t) << 2)
#define PMD_ATTRINDX_MASK	(7 << 2)
#define PMD_ATTRMASK		(PTE_BLOCK_PXN		| \
				 PTE_BLOCK_UXN		| \
				 PMD_ATTRINDX_MASK	| \
				 PTE_TYPE_VALID)

/*
 * TCR flags.
 */
#define TCR_T0SZ(x)		((64 - (x)) << 0)
#define TCR_IRGN_NC		(0 << 8)
#define TCR_IRGN_WBWA		(1 << 8)
#define TCR_IRGN_WT		(2 << 8)
#define TCR_IRGN_WBNWA		(3 << 8)
#define TCR_IRGN_MASK		(3 << 8)
#define TCR_ORGN_NC		(0 << 10)
#define TCR_ORGN_WBWA		(1 << 10)
#define TCR_ORGN_WT		(2 << 10)
#define TCR_ORGN_WBNWA		(3 << 10)
#define TCR_ORGN_MASK		(3 << 10)
#define TCR_SHARED_NON		(0 << 12)
#define TCR_SHARED_OUTER	(2 << 12)
#define TCR_SHARED_INNER	(3 << 12)
#define TCR_TG0_4K		(0 << 14)
#define TCR_TG0_64K		(1 << 14)
#define TCR_TG0_16K		(2 << 14)
#define TCR_EPD1_DISABLE	(1 << 23)

#define TCR_EL1_RSVD		(1 << 31)
#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)

#ifndef __ASSEMBLY__
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
	asm volatile("dsb sy");
	if (el == 1) {
		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	} else if (el == 2) {
		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	} else if (el == 3) {
		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	} else {
		hang();
	}
	asm volatile("isb");
}

struct mm_region {
	u64 virt;
	u64 phys;
	u64 size;
	u64 attrs;
};

extern struct mm_region *mem_map;
void setup_pgtables(void);
u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
#endif

#endif /* _ASM_ARMV8_MMU_H_ */
Commit	Line	Data
0ae76531 DF	1	/*
	2	* (C) Copyright 2013
	3	* David Feng <fenghua@phytium.com.cn>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef _ASM_ARMV8_MMU_H_
	9	#define _ASM_ARMV8_MMU_H_
	10
0ae76531	11	/*
94f7ff36	12	* block/section address mask and size definitions.
0ae76531	13	*/
5e2ec773 AG	14
	15	/* PAGE_SHIFT determines the page size */
	16	#undef PAGE_SIZE
	17	#define PAGE_SHIFT 12
	18	#define PAGE_SIZE (1 << PAGE_SHIFT)
347e30e1	19	#define PAGE_MASK (~(PAGE_SIZE - 1))
5e2ec773	20
0ae76531 DF	21	/***************************************************************/
	22
	23	/*
	24	* Memory types
	25	*/
	26	#define MT_DEVICE_NGNRNE 0
	27	#define MT_DEVICE_NGNRE 1
	28	#define MT_DEVICE_GRE 2
	29	#define MT_NORMAL_NC 3
	30	#define MT_NORMAL 4
	31
94f7ff36 ST	32	#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) \| \
	33	(0x04 << (MT_DEVICE_NGNRE * 8)) \| \
	34	(0x0c << (MT_DEVICE_GRE * 8)) \| \
	35	(0x44 << (MT_NORMAL_NC * 8)) \| \
	36	(UL(0xff) << (MT_NORMAL * 8)))
0ae76531 DF	37
	38	/*
	39	* Hardware page table definitions.
	40	*
94f7ff36 ST	41	*/
94f7ff36 ST	42
5e2ec773 AG	43	#define PTE_TYPE_MASK (3 << 0)
	44	#define PTE_TYPE_FAULT (0 << 0)
	45	#define PTE_TYPE_TABLE (3 << 0)
90351547	46	#define PTE_TYPE_PAGE (3 << 0)
5e2ec773	47	#define PTE_TYPE_BLOCK (1 << 0)
7f9b9f31	48	#define PTE_TYPE_VALID (1 << 0)
94f7ff36	49
5e2ec773 AG	50	#define PTE_TABLE_PXN (1UL << 59)
	51	#define PTE_TABLE_XN (1UL << 60)
	52	#define PTE_TABLE_AP (1UL << 61)
	53	#define PTE_TABLE_NS (1UL << 63)
94f7ff36 ST	54
	55	/*
	56	* Block
	57	*/
5e2ec773	58	#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
7985cdf7	59	#define PTE_BLOCK_NS (1 << 5)
5e2ec773 AG	60	#define PTE_BLOCK_NON_SHARE (0 << 8)
	61	#define PTE_BLOCK_OUTER_SHARE (2 << 8)
	62	#define PTE_BLOCK_INNER_SHARE (3 << 8)
	63	#define PTE_BLOCK_AF (1 << 10)
	64	#define PTE_BLOCK_NG (1 << 11)
	65	#define PTE_BLOCK_PXN (UL(1) << 53)
	66	#define PTE_BLOCK_UXN (UL(1) << 54)
94f7ff36	67
0ae76531 DF	68	/*
	69	* AttrIndx[2:0]
	70	*/
	71	#define PMD_ATTRINDX(t) ((t) << 2)
	72	#define PMD_ATTRINDX_MASK (7 << 2)
7f9b9f31 YS	73	#define PMD_ATTRMASK (PTE_BLOCK_PXN \| \
	74	PTE_BLOCK_UXN \| \
	75	PMD_ATTRINDX_MASK \| \
	76	PTE_TYPE_VALID)
0ae76531 DF	77
	78	/*
	79	* TCR flags.
	80	*/
	81	#define TCR_T0SZ(x) ((64 - (x)) << 0)
	82	#define TCR_IRGN_NC (0 << 8)
	83	#define TCR_IRGN_WBWA (1 << 8)
	84	#define TCR_IRGN_WT (2 << 8)
	85	#define TCR_IRGN_WBNWA (3 << 8)
	86	#define TCR_IRGN_MASK (3 << 8)
	87	#define TCR_ORGN_NC (0 << 10)
	88	#define TCR_ORGN_WBWA (1 << 10)
	89	#define TCR_ORGN_WT (2 << 10)
	90	#define TCR_ORGN_WBNWA (3 << 10)
	91	#define TCR_ORGN_MASK (3 << 10)
	92	#define TCR_SHARED_NON (0 << 12)
21a257b9 ZH	93	#define TCR_SHARED_OUTER (2 << 12)
21a257b9 ZH	94	#define TCR_SHARED_INNER (3 << 12)
0ae76531 DF	95	#define TCR_TG0_4K (0 << 14)
	96	#define TCR_TG0_64K (1 << 14)
	97	#define TCR_TG0_16K (2 << 14)
9bb367a5	98	#define TCR_EPD1_DISABLE (1 << 23)
94f7ff36	99
ad3d6e88 TR	100	#define TCR_EL1_RSVD (1 << 31)
	101	#define TCR_EL2_RSVD (1 << 31 \| 1 << 23)
	102	#define TCR_EL3_RSVD (1 << 31 \| 1 << 23)
	103
22932ffc	104	#ifndef __ASSEMBLY__
22932ffc YS	105	static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
	106	{
	107	asm volatile("dsb sy");
	108	if (el == 1) {
	109	asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
	110	asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
	111	asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
	112	} else if (el == 2) {
	113	asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
	114	asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
	115	asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
	116	} else if (el == 3) {
	117	asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
	118	asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
	119	asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
	120	} else {
	121	hang();
	122	}
	123	asm volatile("isb");
	124	}
94f7ff36 ST	125
94f7ff36 ST	126	struct mm_region {
cd4b0c5f YS	127	u64 virt;
cd4b0c5f YS	128	u64 phys;
94f7ff36 ST	129	u64 size;
	130	u64 attrs;
	131	};
d473f0c6 AG	132
d473f0c6 AG	133	extern struct mm_region *mem_map;
252cdb46 YS	134	void setup_pgtables(void);
252cdb46 YS	135	u64 get_tcr(int el, u64 pips, u64 pva_bits);
22932ffc	136	#endif
94f7ff36	137
0ae76531	138	#endif /* _ASM_ARMV8_MMU_H_ */