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98cb0efd | 1 | /* |
2 | * Copyright 2015 Freescale Semiconductor, Inc. | |
06fb06f6 | 3 | * Copyright 2017 NXP |
98cb0efd | 4 | * |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __FSL_SECURE_BOOT_H | |
9 | #define __FSL_SECURE_BOOT_H | |
10 | ||
bdc22074 | 11 | #ifdef CONFIG_CHAIN_OF_TRUST |
2ed948f4 | 12 | #define CONFIG_FSL_SEC_MON |
2ed948f4 | 13 | |
b63f8a43 | 14 | #ifdef CONFIG_SPL_BUILD |
028ac8c7 SG |
15 | /* |
16 | * Define the key hash for U-Boot here if public/private key pair used to | |
17 | * sign U-boot are different from the SRK hash put in the fuse | |
18 | * Example of defining KEY_HASH is | |
19 | * #define CONFIG_SPL_UBOOT_KEY_HASH \ | |
20 | * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" | |
21 | * else leave it defined as NULL | |
22 | */ | |
23 | ||
24 | #define CONFIG_SPL_UBOOT_KEY_HASH NULL | |
25 | #endif /* ifdef CONFIG_SPL_BUILD */ | |
26 | ||
70f9661c RG |
27 | #define CONFIG_KEY_REVOCATION |
28 | ||
028ac8c7 | 29 | #ifndef CONFIG_SPL_BUILD |
2ed948f4 AB |
30 | #ifndef CONFIG_SYS_RAMBOOT |
31 | /* The key used for verification of next level images | |
32 | * is picked up from an Extension Table which has | |
33 | * been verified by the ISBC (Internal Secure boot Code) | |
34 | * in boot ROM of the SoC. | |
35 | * The feature is only applicable in case of NOR boot and is | |
36 | * not applicable in case of RAMBOOT (NAND, SD, SPI). | |
ac55dadb UA |
37 | * For LS, this feature is available for all device if IE Table |
38 | * is copied to XIP memory | |
39 | * Also, for LS, ISBC doesn't verify this table. | |
2ed948f4 AB |
40 | */ |
41 | #define CONFIG_FSL_ISBC_KEY_EXT | |
2ed948f4 | 42 | |
fd6dbc98 SJ |
43 | #endif |
44 | ||
b3635f57 VPB |
45 | #if defined(CONFIG_FSL_LAYERSCAPE) |
46 | /* | |
47 | * For fsl layerscape based platforms, ESBC image Address in Header | |
48 | * is 64 bit. | |
fcfdb6d5 | 49 | */ |
ef6c55a2 AB |
50 | #define CONFIG_ESBC_ADDR_64BIT |
51 | #endif | |
52 | ||
4a3ab193 | 53 | #ifdef CONFIG_ARCH_LS2080A |
bef238cb SJ |
54 | #define CONFIG_EXTRA_ENV \ |
55 | "setenv fdt_high 0xa0000000;" \ | |
56 | "setenv initrd_high 0xcfffffff;" \ | |
57 | "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" | |
58 | #else | |
98cb0efd | 59 | #define CONFIG_EXTRA_ENV \ |
69d4b48c SG |
60 | "setenv fdt_high 0xffffffff;" \ |
61 | "setenv initrd_high 0xffffffff;" \ | |
98cb0efd | 62 | "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" |
bef238cb | 63 | #endif |
98cb0efd | 64 | |
3f701cc5 SJ |
65 | /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from |
66 | * Non-XIP Memory (Nand/SD)*/ | |
39199356 | 67 | #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ |
762f92a6 | 68 | defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) |
3f701cc5 SJ |
69 | #define CONFIG_BOOTSCRIPT_COPY_RAM |
70 | #endif | |
69d4b48c SG |
71 | /* The address needs to be modified according to NOR, NAND, SD and |
72 | * DDR memory map | |
73 | */ | |
39199356 | 74 | #ifdef CONFIG_FSL_LSCH3 |
06fb06f6 SG |
75 | #define CONFIG_BS_ADDR_DEVICE 0x580600000 |
76 | #define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000 | |
69d4b48c | 77 | #define CONFIG_BS_SIZE 0x00001000 |
06fb06f6 SG |
78 | #define CONFIG_BS_HDR_SIZE 0x00004000 |
79 | #define CONFIG_BS_ADDR_RAM 0xa0600000 | |
80 | #define CONFIG_BS_HDR_ADDR_RAM 0xa0640000 | |
69d4b48c SG |
81 | #else |
82 | #ifdef CONFIG_SD_BOOT | |
83 | /* For SD boot address and size are assigned in terms of sector | |
84 | * offset and no. of sectors respectively. | |
85 | */ | |
06fb06f6 SG |
86 | #define CONFIG_BS_ADDR_DEVICE 0x00003000 |
87 | #define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200 | |
69d4b48c | 88 | #define CONFIG_BS_SIZE 0x00000008 |
06fb06f6 | 89 | #define CONFIG_BS_HDR_SIZE 0x00000010 |
762f92a6 | 90 | #elif defined(CONFIG_NAND_BOOT) |
06fb06f6 SG |
91 | #define CONFIG_BS_ADDR_DEVICE 0x00600000 |
92 | #define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000 | |
93 | #define CONFIG_BS_SIZE 0x00001000 | |
b3635f57 | 94 | #define CONFIG_BS_HDR_SIZE 0x00002000 |
06fb06f6 SG |
95 | #elif defined(CONFIG_QSPI_BOOT) |
96 | #define CONFIG_BS_ADDR_DEVICE 0x40600000 | |
97 | #define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000 | |
b3635f57 | 98 | #define CONFIG_BS_SIZE 0x00001000 |
69d4b48c | 99 | #define CONFIG_BS_HDR_SIZE 0x00002000 |
06fb06f6 SG |
100 | #else /* Default NOR Boot */ |
101 | #define CONFIG_BS_ADDR_DEVICE 0x60600000 | |
102 | #define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000 | |
69d4b48c | 103 | #define CONFIG_BS_SIZE 0x00001000 |
06fb06f6 | 104 | #define CONFIG_BS_HDR_SIZE 0x00002000 |
b3635f57 | 105 | #endif |
06fb06f6 SG |
106 | #define CONFIG_BS_ADDR_RAM 0x81000000 |
107 | #define CONFIG_BS_HDR_ADDR_RAM 0x81020000 | |
3f701cc5 SJ |
108 | #endif |
109 | ||
110 | #ifdef CONFIG_BOOTSCRIPT_COPY_RAM | |
3f701cc5 | 111 | #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM |
06fb06f6 | 112 | #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM |
216e93a1 | 113 | #else |
69d4b48c SG |
114 | #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE |
115 | /* BOOTSCRIPT_ADDR is not required */ | |
216e93a1 | 116 | #endif |
98cb0efd | 117 | |
07806e62 | 118 | #ifdef CONFIG_FSL_LS_PPA |
07806e62 SG |
119 | /* Define the key hash here if SRK used for signing PPA image is |
120 | * different from SRK hash put in SFP used for U-Boot. | |
121 | * Example | |
d1a795ac | 122 | * #define PPA_KEY_HASH \ |
07806e62 SG |
123 | * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" |
124 | */ | |
d1a795ac | 125 | #define PPA_KEY_HASH NULL |
07806e62 SG |
126 | #endif /* ifdef CONFIG_FSL_LS_PPA */ |
127 | ||
bdc22074 | 128 | #include <config_fsl_chain_trust.h> |
028ac8c7 | 129 | #endif /* #ifndef CONFIG_SPL_BUILD */ |
bdc22074 | 130 | #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ |
98cb0efd | 131 | #endif |