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Convert CONFIG_CMD_HASH to Kconfig
[people/ms/u-boot.git] / arch / arm / include / asm / fsl_secure_boot.h
CommitLineData
98cb0efd 1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __FSL_SECURE_BOOT_H
8#define __FSL_SECURE_BOOT_H
9
bdc22074 10#ifdef CONFIG_CHAIN_OF_TRUST
2ed948f4 11#define CONFIG_FSL_SEC_MON
2ed948f4 12
b63f8a43 13#ifdef CONFIG_SPL_BUILD
028ac8c7
SG
14/*
15 * Define the key hash for U-Boot here if public/private key pair used to
16 * sign U-boot are different from the SRK hash put in the fuse
17 * Example of defining KEY_HASH is
18 * #define CONFIG_SPL_UBOOT_KEY_HASH \
19 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
20 * else leave it defined as NULL
21 */
22
23#define CONFIG_SPL_UBOOT_KEY_HASH NULL
24#endif /* ifdef CONFIG_SPL_BUILD */
25
70f9661c
RG
26#define CONFIG_KEY_REVOCATION
27
028ac8c7 28#ifndef CONFIG_SPL_BUILD
2ed948f4
AB
29#ifndef CONFIG_SYS_RAMBOOT
30/* The key used for verification of next level images
31 * is picked up from an Extension Table which has
32 * been verified by the ISBC (Internal Secure boot Code)
33 * in boot ROM of the SoC.
34 * The feature is only applicable in case of NOR boot and is
35 * not applicable in case of RAMBOOT (NAND, SD, SPI).
ac55dadb
UA
36 * For LS, this feature is available for all device if IE Table
37 * is copied to XIP memory
38 * Also, for LS, ISBC doesn't verify this table.
2ed948f4
AB
39 */
40#define CONFIG_FSL_ISBC_KEY_EXT
2ed948f4 41
fd6dbc98
SJ
42#endif
43
b3635f57
VPB
44#if defined(CONFIG_FSL_LAYERSCAPE)
45/*
46 * For fsl layerscape based platforms, ESBC image Address in Header
47 * is 64 bit.
fcfdb6d5 48 */
ef6c55a2
AB
49#define CONFIG_ESBC_ADDR_64BIT
50#endif
51
4a3ab193 52#ifdef CONFIG_ARCH_LS2080A
bef238cb
SJ
53#define CONFIG_EXTRA_ENV \
54 "setenv fdt_high 0xa0000000;" \
55 "setenv initrd_high 0xcfffffff;" \
56 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
57#else
98cb0efd 58#define CONFIG_EXTRA_ENV \
69d4b48c
SG
59 "setenv fdt_high 0xffffffff;" \
60 "setenv initrd_high 0xffffffff;" \
98cb0efd 61 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
bef238cb 62#endif
98cb0efd 63
3f701cc5
SJ
64/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
65 * Non-XIP Memory (Nand/SD)*/
39199356 66#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
762f92a6 67 defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT)
3f701cc5
SJ
68#define CONFIG_BOOTSCRIPT_COPY_RAM
69#endif
69d4b48c
SG
70/* The address needs to be modified according to NOR, NAND, SD and
71 * DDR memory map
72 */
39199356
UA
73#ifdef CONFIG_FSL_LSCH3
74#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000
75#define CONFIG_BS_ADDR_DEVICE 0x580e00000
76#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000
77#define CONFIG_BS_ADDR_RAM 0xa0e00000
69d4b48c
SG
78#define CONFIG_BS_HDR_SIZE 0x00002000
79#define CONFIG_BS_SIZE 0x00001000
80#else
81#ifdef CONFIG_SD_BOOT
82/* For SD boot address and size are assigned in terms of sector
83 * offset and no. of sectors respectively.
84 */
c1303bfd 85#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
70f9661c
RG
86#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920
87#else
88#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
89#endif
9b6639fa 90#define CONFIG_BS_ADDR_DEVICE 0x00000940
69d4b48c
SG
91#define CONFIG_BS_HDR_SIZE 0x00000010
92#define CONFIG_BS_SIZE 0x00000008
762f92a6
RG
93#elif defined(CONFIG_NAND_BOOT)
94#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
95#define CONFIG_BS_ADDR_DEVICE 0x00802000
96#define CONFIG_BS_HDR_SIZE 0x00002000
97#define CONFIG_BS_SIZE 0x00001000
b3635f57
VPB
98#elif defined(CONFIG_QSPI_BOOT)
99#ifdef CONFIG_ARCH_LS1046A
100#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000
101#define CONFIG_BS_ADDR_DEVICE 0x40800000
d2a99502
VPB
102#elif defined(CONFIG_ARCH_LS1012A)
103#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000
104#define CONFIG_BS_ADDR_DEVICE 0x40060000
3f701cc5 105#else
b3635f57
VPB
106#error "Platform not supported"
107#endif
108#define CONFIG_BS_HDR_SIZE 0x00002000
109#define CONFIG_BS_SIZE 0x00001000
110#else /* Default NOR Boot */
69d4b48c
SG
111#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
112#define CONFIG_BS_ADDR_DEVICE 0x60060000
113#define CONFIG_BS_HDR_SIZE 0x00002000
114#define CONFIG_BS_SIZE 0x00001000
b3635f57 115#endif
69d4b48c
SG
116#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
117#define CONFIG_BS_ADDR_RAM 0x81020000
3f701cc5
SJ
118#endif
119
120#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
121#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
3f701cc5 122#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
216e93a1 123#else
69d4b48c
SG
124#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
125/* BOOTSCRIPT_ADDR is not required */
216e93a1 126#endif
98cb0efd 127
07806e62 128#ifdef CONFIG_FSL_LS_PPA
07806e62
SG
129/* Define the key hash here if SRK used for signing PPA image is
130 * different from SRK hash put in SFP used for U-Boot.
131 * Example
d1a795ac 132 * #define PPA_KEY_HASH \
07806e62
SG
133 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
134 */
d1a795ac 135#define PPA_KEY_HASH NULL
07806e62
SG
136#endif /* ifdef CONFIG_FSL_LS_PPA */
137
bdc22074 138#include <config_fsl_chain_trust.h>
028ac8c7 139#endif /* #ifndef CONFIG_SPL_BUILD */
bdc22074 140#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
98cb0efd 141#endif