[people/ms/u-boot.git] / arch / arm / include / asm / system.h

#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H

#include <common.h>
#include <linux/compiler.h>
#include <asm/barriers.h>

#ifdef CONFIG_ARM64

/*
 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
 */
#define CR_M		(1 << 0)	/* MMU enable			*/
#define CR_A		(1 << 1)	/* Alignment abort enable	*/
#define CR_C		(1 << 2)	/* Dcache enable		*/
#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
#define CR_I		(1 << 12)	/* Icache enable		*/
#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/

#ifndef __ASSEMBLY__

u64 get_page_table_size(void);
#define PGTABLE_SIZE	get_page_table_size()

/* 2MB granularity */
#define MMU_SECTION_SHIFT	21
#define MMU_SECTION_SIZE	(1 << MMU_SECTION_SHIFT)

/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
enum dcache_option {
	DCACHE_OFF = 0 << 2,
	DCACHE_WRITETHROUGH = 3 << 2,
	DCACHE_WRITEBACK = 4 << 2,
	DCACHE_WRITEALLOC = 4 << 2,
};

#define wfi()				\
	({asm volatile(			\
	"wfi" : : : "memory");		\
	})

static inline unsigned int current_el(void)
{
	unsigned int el;
	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
	return el >> 2;
}

static inline unsigned int get_sctlr(void)
{
	unsigned int el, val;

	el = current_el();
	if (el == 1)
		asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
	else if (el == 2)
		asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
	else
		asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");

	return val;
}

static inline void set_sctlr(unsigned int val)
{
	unsigned int el;

	el = current_el();
	if (el == 1)
		asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
	else if (el == 2)
		asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
	else
		asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");

	asm volatile("isb");
}

static inline unsigned long read_mpidr(void)
{
	unsigned long val;

	asm volatile("mrs %0, mpidr_el1" : "=r" (val));

	return val;
}

#define BSP_COREID	0

void __asm_flush_dcache_all(void);
void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
int __asm_flush_l3_cache(void);
void __asm_switch_ttbr(u64 new_ttbr);

void armv8_switch_to_el2(void);
void armv8_switch_to_el1(void);
void gic_init(void);
void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
void protect_secure_region(void);
void smp_kick_all_cpus(void);

void flush_l3_cache(void);

/*
 *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
 * DEN0028A
 *
 * @args: input and output arguments
 *
 */
void smc_call(struct pt_regs *args);

void __noreturn psci_system_reset(void);
void __noreturn psci_system_off(void);

#endif	/* __ASSEMBLY__ */

#else /* CONFIG_ARM64 */

#ifdef __KERNEL__

#define CPU_ARCH_UNKNOWN	0
#define CPU_ARCH_ARMv3		1
#define CPU_ARCH_ARMv4		2
#define CPU_ARCH_ARMv4T		3
#define CPU_ARCH_ARMv5		4
#define CPU_ARCH_ARMv5T		5
#define CPU_ARCH_ARMv5TE	6
#define CPU_ARCH_ARMv5TEJ	7
#define CPU_ARCH_ARMv6		8
#define CPU_ARCH_ARMv7		9

/*
 * CR1 bits (CP#15 CR1)
 */
#define CR_M	(1 << 0)	/* MMU enable				*/
#define CR_A	(1 << 1)	/* Alignment abort enable		*/
#define CR_C	(1 << 2)	/* Dcache enable			*/
#define CR_W	(1 << 3)	/* Write buffer enable			*/
#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
#define CR_D	(1 << 5)	/* 32-bit data address range		*/
#define CR_L	(1 << 6)	/* Implementation defined		*/
#define CR_B	(1 << 7)	/* Big endian				*/
#define CR_S	(1 << 8)	/* System MMU protection		*/
#define CR_R	(1 << 9)	/* ROM MMU protection			*/
#define CR_F	(1 << 10)	/* Implementation defined		*/
#define CR_Z	(1 << 11)	/* Implementation defined		*/
#define CR_I	(1 << 12)	/* Icache enable			*/
#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
#define CR_DT	(1 << 16)
#define CR_IT	(1 << 18)
#define CR_ST	(1 << 19)
#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
#define CR_U	(1 << 22)	/* Unaligned access operation		*/
#define CR_XP	(1 << 23)	/* Extended page tables			*/
#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
#define CR_AFE	(1 << 29)	/* Access flag enable			*/
#define CR_TE	(1 << 30)	/* Thumb exception enable		*/

#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
#define PGTABLE_SIZE		(4096 * 5)
#elif !defined(PGTABLE_SIZE)
#define PGTABLE_SIZE		(4096 * 4)
#endif

/*
 * This is used to ensure the compiler did actually allocate the register we
 * asked it for some inline assembly sequences.  Apparently we can't trust
 * the compiler from one version to another so a bit of paranoia won't hurt.
 * This string is meant to be concatenated with the inline asm string and
 * will cause compilation to stop on mismatch.
 * (for details, see gcc PR 15089)
 */
#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"

#ifndef __ASSEMBLY__

/**
 * save_boot_params() - Save boot parameters before starting reset sequence
 *
 * If you provide this function it will be called immediately U-Boot starts,
 * both for SPL and U-Boot proper.
 *
 * All registers are unchanged from U-Boot entry. No registers need be
 * preserved.
 *
 * This is not a normal C function. There is no stack. Return by branching to
 * save_boot_params_ret.
 *
 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
 */

/**
 * save_boot_params_ret() - Return from save_boot_params()
 *
 * If you provide save_boot_params(), then you should jump back to this
 * function when done. Try to preserve all registers.
 *
 * If your implementation of save_boot_params() is in C then it is acceptable
 * to simply call save_boot_params_ret() at the end of your function. Since
 * there is no link register set up, you cannot just exit the function. U-Boot
 * will return to the (initialised) value of lr, and likely crash/hang.
 *
 * If your implementation of save_boot_params() is in assembler then you
 * should use 'b' or 'bx' to return to save_boot_params_ret.
 */
void save_boot_params_ret(void);

#ifdef CONFIG_ARMV7_LPAE
void switch_to_hypervisor_ret(void);
#endif

#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

#ifdef __ARM_ARCH_7A__
#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
#else
#define wfi()
#endif

static inline unsigned long get_cpsr(void)
{
	unsigned long cpsr;

	asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
	return cpsr;
}

static inline int is_hyp(void)
{
#ifdef CONFIG_ARMV7_LPAE
	/* HYP mode requires LPAE ... */
	return ((get_cpsr() & 0x1f) == 0x1a);
#else
	/* ... so without LPAE support we can optimize all hyp code away */
	return 0;
#endif
}

static inline unsigned int get_cr(void)
{
	unsigned int val;

	if (is_hyp())
		asm volatile("mrc p15, 4, %0, c1, c0, 0	@ get CR" : "=r" (val)
								  :
								  : "cc");
	else
		asm volatile("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val)
								  :
								  : "cc");
	return val;
}

static inline void set_cr(unsigned int val)
{
	if (is_hyp())
		asm volatile("mcr p15, 4, %0, c1, c0, 0	@ set CR" :
								  : "r" (val)
								  : "cc");
	else
		asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR" :
								  : "r" (val)
								  : "cc");
	isb();
}

static inline unsigned int get_dacr(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c3, c0, 0	@ get DACR" : "=r" (val) : : "cc");
	return val;
}

static inline void set_dacr(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c3, c0, 0	@ set DACR"
	  : : "r" (val) : "cc");
	isb();
}

#ifdef CONFIG_ARMV7_LPAE
/* Long-Descriptor Translation Table Level 1/2 Bits */
#define TTB_SECT_XN_MASK	(1ULL << 54)
#define TTB_SECT_NG_MASK	(1 << 11)
#define TTB_SECT_AF		(1 << 10)
#define TTB_SECT_SH_MASK	(3 << 8)
#define TTB_SECT_NS_MASK	(1 << 5)
#define TTB_SECT_AP		(1 << 6)
/* Note: TTB AP bits are set elsewhere */
#define TTB_SECT_MAIR(x)	((x & 0x7) << 2) /* Index into MAIR */
#define TTB_SECT		(1 << 0)
#define TTB_PAGETABLE		(3 << 0)

/* TTBCR flags */
#define TTBCR_EAE		(1 << 31)
#define TTBCR_T0SZ(x)		((x) << 0)
#define TTBCR_T1SZ(x)		((x) << 16)
#define TTBCR_USING_TTBR0	(TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
#define TTBCR_IRGN0_NC		(0 << 8)
#define TTBCR_IRGN0_WBWA	(1 << 8)
#define TTBCR_IRGN0_WT		(2 << 8)
#define TTBCR_IRGN0_WBNWA	(3 << 8)
#define TTBCR_IRGN0_MASK	(3 << 8)
#define TTBCR_ORGN0_NC		(0 << 10)
#define TTBCR_ORGN0_WBWA	(1 << 10)
#define TTBCR_ORGN0_WT		(2 << 10)
#define TTBCR_ORGN0_WBNWA	(3 << 10)
#define TTBCR_ORGN0_MASK	(3 << 10)
#define TTBCR_SHARED_NON	(0 << 12)
#define TTBCR_SHARED_OUTER	(2 << 12)
#define TTBCR_SHARED_INNER	(3 << 12)
#define TTBCR_EPD0		(0 << 7)

/*
 * Memory types
 */
#define MEMORY_ATTRIBUTES	((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
				 (0xcc << (2 * 8)) | (0xff << (3 * 8)))

/* options available for data cache on each page */
enum dcache_option {
	DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
	DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
	DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
	DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
};
#elif defined(CONFIG_CPU_V7)
/* Short-Descriptor Translation Table Level 1 Bits */
#define TTB_SECT_NS_MASK	(1 << 19)
#define TTB_SECT_NG_MASK	(1 << 17)
#define TTB_SECT_S_MASK		(1 << 16)
/* Note: TTB AP bits are set elsewhere */
#define TTB_SECT_AP		(3 << 10)
#define TTB_SECT_TEX(x)		((x & 0x7) << 12)
#define TTB_SECT_DOMAIN(x)	((x & 0xf) << 5)
#define TTB_SECT_XN_MASK	(1 << 4)
#define TTB_SECT_C_MASK		(1 << 3)
#define TTB_SECT_B_MASK		(1 << 2)
#define TTB_SECT			(2 << 0)

/* options available for data cache on each page */
enum dcache_option {
	DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
	DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
};
#else
#define TTB_SECT_AP		(3 << 10)
/* options available for data cache on each page */
enum dcache_option {
	DCACHE_OFF = 0x12,
	DCACHE_WRITETHROUGH = 0x1a,
	DCACHE_WRITEBACK = 0x1e,
	DCACHE_WRITEALLOC = 0x16,
};
#endif

/* Size of an MMU section */
enum {
#ifdef CONFIG_ARMV7_LPAE
	MMU_SECTION_SHIFT	= 21, /* 2MB */
#else
	MMU_SECTION_SHIFT	= 20, /* 1MB */
#endif
	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
};

#ifdef CONFIG_CPU_V7
/* TTBR0 bits */
#define TTBR0_BASE_ADDR_MASK	0xFFFFC000
#define TTBR0_RGN_NC			(0 << 3)
#define TTBR0_RGN_WBWA			(1 << 3)
#define TTBR0_RGN_WT			(2 << 3)
#define TTBR0_RGN_WB			(3 << 3)
/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
#define TTBR0_IRGN_NC			(0 << 0 | 0 << 6)
#define TTBR0_IRGN_WBWA			(0 << 0 | 1 << 6)
#define TTBR0_IRGN_WT			(1 << 0 | 0 << 6)
#define TTBR0_IRGN_WB			(1 << 0 | 1 << 6)
#endif

/**
 * Register an update to the page tables, and flush the TLB
 *
 * \param start		start address of update in page table
 * \param stop		stop address of update in page table
 */
void mmu_page_table_flush(unsigned long start, unsigned long stop);

#endif /* __ASSEMBLY__ */

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif /* CONFIG_ARM64 */

#ifndef __ASSEMBLY__
/**
 * Change the cache settings for a region.
 *
 * \param start		start address of memory region to change
 * \param size		size of memory region to change
 * \param option	dcache option to select
 */
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
				     enum dcache_option option);

#ifdef CONFIG_SYS_NONCACHED_MEMORY
void noncached_init(void);
phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_SYS_NONCACHED_MEMORY */

#endif /* __ASSEMBLY__ */

#endif
Commit	Line	Data
677e62f4 JCPV	1	#ifndef __ASM_ARM_SYSTEM_H
	2	#define __ASM_ARM_SYSTEM_H
	3
a5b9fa30 ST	4	#include <common.h>
a5b9fa30 ST	5	#include <linux/compiler.h>
a78cd861	6	#include <asm/barriers.h>
a5b9fa30	7
0ae76531 DF	8	#ifdef CONFIG_ARM64
	9
	10	/*
	11	* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
	12	*/
	13	#define CR_M (1 << 0) /* MMU enable */
	14	#define CR_A (1 << 1) /* Alignment abort enable */
	15	#define CR_C (1 << 2) /* Dcache enable */
	16	#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
	17	#define CR_I (1 << 12) /* Icache enable */
	18	#define CR_WXN (1 << 19) /* Write Permision Imply XN */
	19	#define CR_EE (1 << 25) /* Exception (Big) Endian */
	20
0ae76531 DF	21	#ifndef __ASSEMBLY__
0ae76531 DF	22
5e2ec773 AG	23	u64 get_page_table_size(void);
5e2ec773 AG	24	#define PGTABLE_SIZE get_page_table_size()
7985cdf7 AG	25
	26	/* 2MB granularity */
	27	#define MMU_SECTION_SHIFT 21
	28	#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
5e2ec773	29
53eb45ef	30	/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
dad17fd5	31	enum dcache_option {
53eb45ef AG	32	DCACHE_OFF = 0 << 2,
	33	DCACHE_WRITETHROUGH = 3 << 2,
	34	DCACHE_WRITEBACK = 4 << 2,
	35	DCACHE_WRITEALLOC = 4 << 2,
dad17fd5 SDPP	36	};
dad17fd5 SDPP	37
0ae76531 DF	38	#define wfi() \
	39	({asm volatile( \
	40	"wfi" : : : "memory"); \
	41	})
	42
	43	static inline unsigned int current_el(void)
	44	{
	45	unsigned int el;
	46	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
	47	return el >> 2;
	48	}
	49
	50	static inline unsigned int get_sctlr(void)
	51	{
	52	unsigned int el, val;
	53
	54	el = current_el();
	55	if (el == 1)
	56	asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
	57	else if (el == 2)
	58	asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
	59	else
	60	asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
	61
	62	return val;
	63	}
	64
	65	static inline void set_sctlr(unsigned int val)
	66	{
	67	unsigned int el;
	68
	69	el = current_el();
	70	if (el == 1)
	71	asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
	72	else if (el == 2)
	73	asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
	74	else
	75	asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
	76
	77	asm volatile("isb");
	78	}
	79
ba5648cd ST	80	static inline unsigned long read_mpidr(void)
	81	{
	82	unsigned long val;
	83
	84	asm volatile("mrs %0, mpidr_el1" : "=r" (val));
	85
	86	return val;
	87	}
	88
	89	#define BSP_COREID 0
	90
0ae76531	91	void __asm_flush_dcache_all(void);
1e6ad55c	92	void __asm_invalidate_dcache_all(void);
0ae76531 DF	93	void __asm_flush_dcache_range(u64 start, u64 end);
	94	void __asm_invalidate_tlb_all(void);
	95	void __asm_invalidate_icache_all(void);
dcd468b8	96	int __asm_flush_l3_cache(void);
5e2ec773	97	void __asm_switch_ttbr(u64 new_ttbr);
0ae76531 DF	98
	99	void armv8_switch_to_el2(void);
	100	void armv8_switch_to_el1(void);
	101	void gic_init(void);
	102	void gic_send_sgi(unsigned long sgino);
	103	void wait_for_wakeup(void);
73169874	104	void protect_secure_region(void);
0ae76531 DF	105	void smp_kick_all_cpus(void);
0ae76531 DF	106
2f78eae5 YS	107	void flush_l3_cache(void);
2f78eae5 YS	108
a5b9fa30 ST	109	/*
	110	*Issue a secure monitor call in accordance with ARM "SMC Calling convention",
	111	* DEN0028A
	112	*
	113	* @args: input and output arguments
	114	*
	115	*/
	116	void smc_call(struct pt_regs *args);
	117
51bfb5b6	118	void __noreturn psci_system_reset(void);
3ee655ed	119	void __noreturn psci_system_off(void);
5a07abb3	120
0ae76531 DF	121	#endif /* __ASSEMBLY__ */
	122
	123	#else /* CONFIG_ARM64 */
	124
677e62f4 JCPV	125	#ifdef __KERNEL__
	126
	127	#define CPU_ARCH_UNKNOWN 0
	128	#define CPU_ARCH_ARMv3 1
	129	#define CPU_ARCH_ARMv4 2
	130	#define CPU_ARCH_ARMv4T 3
	131	#define CPU_ARCH_ARMv5 4
	132	#define CPU_ARCH_ARMv5T 5
	133	#define CPU_ARCH_ARMv5TE 6
	134	#define CPU_ARCH_ARMv5TEJ 7
	135	#define CPU_ARCH_ARMv6 8
	136	#define CPU_ARCH_ARMv7 9
	137
	138	/*
	139	* CR1 bits (CP#15 CR1)
	140	*/
	141	#define CR_M (1 << 0) /* MMU enable */
	142	#define CR_A (1 << 1) /* Alignment abort enable */
	143	#define CR_C (1 << 2) /* Dcache enable */
	144	#define CR_W (1 << 3) /* Write buffer enable */
	145	#define CR_P (1 << 4) /* 32-bit exception handler */
	146	#define CR_D (1 << 5) /* 32-bit data address range */
	147	#define CR_L (1 << 6) /* Implementation defined */
	148	#define CR_B (1 << 7) /* Big endian */
	149	#define CR_S (1 << 8) /* System MMU protection */
	150	#define CR_R (1 << 9) /* ROM MMU protection */
	151	#define CR_F (1 << 10) /* Implementation defined */
	152	#define CR_Z (1 << 11) /* Implementation defined */
	153	#define CR_I (1 << 12) /* Icache enable */
	154	#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
	155	#define CR_RR (1 << 14) /* Round Robin cache replacement */
	156	#define CR_L4 (1 << 15) /* LDR pc can set T bit */
	157	#define CR_DT (1 << 16)
	158	#define CR_IT (1 << 18)
	159	#define CR_ST (1 << 19)
	160	#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
	161	#define CR_U (1 << 22) /* Unaligned access operation */
	162	#define CR_XP (1 << 23) /* Extended page tables */
	163	#define CR_VE (1 << 24) /* Vectored interrupts */
	164	#define CR_EE (1 << 25) /* Exception (Big) Endian */
	165	#define CR_TRE (1 << 28) /* TEX remap enable */
	166	#define CR_AFE (1 << 29) /* Access flag enable */
	167	#define CR_TE (1 << 30) /* Thumb exception enable */
	168
d990f5c8 AG	169	#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
	170	#define PGTABLE_SIZE (4096 * 5)
	171	#elif !defined(PGTABLE_SIZE)
0ae76531	172	#define PGTABLE_SIZE (4096 * 4)
94f7ff36	173	#endif
0ae76531	174
677e62f4 JCPV	175	/*
	176	* This is used to ensure the compiler did actually allocate the register we
	177	* asked it for some inline assembly sequences. Apparently we can't trust
	178	* the compiler from one version to another so a bit of paranoia won't hurt.
	179	* This string is meant to be concatenated with the inline asm string and
	180	* will cause compilation to stop on mismatch.
	181	* (for details, see gcc PR 15089)
	182	*/
	183	#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
	184
	185	#ifndef __ASSEMBLY__
	186
e11c6c27 SG	187	/**
	188	* save_boot_params() - Save boot parameters before starting reset sequence
	189	*
	190	* If you provide this function it will be called immediately U-Boot starts,
	191	* both for SPL and U-Boot proper.
	192	*
	193	* All registers are unchanged from U-Boot entry. No registers need be
	194	* preserved.
	195	*
	196	* This is not a normal C function. There is no stack. Return by branching to
	197	* save_boot_params_ret.
	198	*
	199	* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
	200	*/
	201
55199121 SG	202	/**
	203	* save_boot_params_ret() - Return from save_boot_params()
	204	*
	205	* If you provide save_boot_params(), then you should jump back to this
	206	* function when done. Try to preserve all registers.
	207	*
	208	* If your implementation of save_boot_params() is in C then it is acceptable
	209	* to simply call save_boot_params_ret() at the end of your function. Since
	210	* there is no link register set up, you cannot just exit the function. U-Boot
	211	* will return to the (initialised) value of lr, and likely crash/hang.
	212	*
	213	* If your implementation of save_boot_params() is in assembler then you
	214	* should use 'b' or 'bx' to return to save_boot_params_ret.
	215	*/
	216	void save_boot_params_ret(void);
	217
d31d4a2d K	218	#ifdef CONFIG_ARMV7_LPAE
	219	void switch_to_hypervisor_ret(void);
	220	#endif
	221
677e62f4 JCPV	222	#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
677e62f4 JCPV	223
2ff467c0 RH	224	#ifdef __ARM_ARCH_7A__
	225	#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
	226	#else
	227	#define wfi()
	228	#endif
	229
d990f5c8 AG	230	static inline unsigned long get_cpsr(void)
	231	{
	232	unsigned long cpsr;
	233
	234	asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
	235	return cpsr;
	236	}
	237
	238	static inline int is_hyp(void)
	239	{
	240	#ifdef CONFIG_ARMV7_LPAE
	241	/* HYP mode requires LPAE ... */
	242	return ((get_cpsr() & 0x1f) == 0x1a);
	243	#else
	244	/* ... so without LPAE support we can optimize all hyp code away */
	245	return 0;
	246	#endif
	247	}
	248
677e62f4 JCPV	249	static inline unsigned int get_cr(void)
	250	{
	251	unsigned int val;
d990f5c8 AG	252
	253	if (is_hyp())
	254	asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
	255	:
	256	: "cc");
	257	else
	258	asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
	259	:
	260	: "cc");
677e62f4 JCPV	261	return val;
	262	}
	263
	264	static inline void set_cr(unsigned int val)
	265	{
d990f5c8 AG	266	if (is_hyp())
	267	asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
	268	: "r" (val)
	269	: "cc");
	270	else
	271	asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
	272	: "r" (val)
	273	: "cc");
677e62f4 JCPV	274	isb();
	275	}
	276
de63ac27 S	277	static inline unsigned int get_dacr(void)
	278	{
	279	unsigned int val;
	280	asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
	281	return val;
	282	}
	283
	284	static inline void set_dacr(unsigned int val)
	285	{
	286	asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
	287	: : "r" (val) : "cc");
	288	isb();
	289	}
	290
d990f5c8 AG	291	#ifdef CONFIG_ARMV7_LPAE
	292	/* Long-Descriptor Translation Table Level 1/2 Bits */
	293	#define TTB_SECT_XN_MASK (1ULL << 54)
	294	#define TTB_SECT_NG_MASK (1 << 11)
	295	#define TTB_SECT_AF (1 << 10)
	296	#define TTB_SECT_SH_MASK (3 << 8)
	297	#define TTB_SECT_NS_MASK (1 << 5)
	298	#define TTB_SECT_AP (1 << 6)
	299	/* Note: TTB AP bits are set elsewhere */
	300	#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
	301	#define TTB_SECT (1 << 0)
	302	#define TTB_PAGETABLE (3 << 0)
	303
	304	/* TTBCR flags */
	305	#define TTBCR_EAE (1 << 31)
	306	#define TTBCR_T0SZ(x) ((x) << 0)
	307	#define TTBCR_T1SZ(x) ((x) << 16)
	308	#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) \| TTBCR_T1SZ(0))
	309	#define TTBCR_IRGN0_NC (0 << 8)
	310	#define TTBCR_IRGN0_WBWA (1 << 8)
	311	#define TTBCR_IRGN0_WT (2 << 8)
	312	#define TTBCR_IRGN0_WBNWA (3 << 8)
	313	#define TTBCR_IRGN0_MASK (3 << 8)
	314	#define TTBCR_ORGN0_NC (0 << 10)
	315	#define TTBCR_ORGN0_WBWA (1 << 10)
	316	#define TTBCR_ORGN0_WT (2 << 10)
	317	#define TTBCR_ORGN0_WBNWA (3 << 10)
	318	#define TTBCR_ORGN0_MASK (3 << 10)
	319	#define TTBCR_SHARED_NON (0 << 12)
	320	#define TTBCR_SHARED_OUTER (2 << 12)
	321	#define TTBCR_SHARED_INNER (3 << 12)
	322	#define TTBCR_EPD0 (0 << 7)
	323
	324	/*
	325	* Memory types
	326	*/
	327	#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) \| (0x88 << (1 * 8)) \| \
	328	(0xcc << (2 * 8)) \| (0xff << (3 * 8)))
	329
	330	/* options available for data cache on each page */
	331	enum dcache_option {
	332	DCACHE_OFF = TTB_SECT \| TTB_SECT_MAIR(0),
	333	DCACHE_WRITETHROUGH = TTB_SECT \| TTB_SECT_MAIR(1),
	334	DCACHE_WRITEBACK = TTB_SECT \| TTB_SECT_MAIR(2),
	335	DCACHE_WRITEALLOC = TTB_SECT \| TTB_SECT_MAIR(3),
	336	};
	337	#elif defined(CONFIG_CPU_V7)
97840b5d BB	338	/* Short-Descriptor Translation Table Level 1 Bits */
	339	#define TTB_SECT_NS_MASK (1 << 19)
	340	#define TTB_SECT_NG_MASK (1 << 17)
	341	#define TTB_SECT_S_MASK (1 << 16)
	342	/* Note: TTB AP bits are set elsewhere */
d990f5c8	343	#define TTB_SECT_AP (3 << 10)
97840b5d BB	344	#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
	345	#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
	346	#define TTB_SECT_XN_MASK (1 << 4)
	347	#define TTB_SECT_C_MASK (1 << 3)
	348	#define TTB_SECT_B_MASK (1 << 2)
	349	#define TTB_SECT (2 << 0)
	350
	351	/* options available for data cache on each page */
	352	enum dcache_option {
8890c2fb	353	DCACHE_OFF = TTB_SECT_DOMAIN(0) \| TTB_SECT_XN_MASK \| TTB_SECT,
97840b5d BB	354	DCACHE_WRITETHROUGH = DCACHE_OFF \| TTB_SECT_C_MASK,
	355	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH \| TTB_SECT_B_MASK,
	356	DCACHE_WRITEALLOC = DCACHE_WRITEBACK \| TTB_SECT_TEX(1),
	357	};
	358	#else
d990f5c8	359	#define TTB_SECT_AP (3 << 10)
0dde7f53 SG	360	/* options available for data cache on each page */
	361	enum dcache_option {
	362	DCACHE_OFF = 0x12,
	363	DCACHE_WRITETHROUGH = 0x1a,
	364	DCACHE_WRITEBACK = 0x1e,
ff7e9700	365	DCACHE_WRITEALLOC = 0x16,
0dde7f53	366	};
97840b5d	367	#endif
0dde7f53 SG	368
	369	/* Size of an MMU section */
	370	enum {
d990f5c8 AG	371	#ifdef CONFIG_ARMV7_LPAE
	372	MMU_SECTION_SHIFT = 21, /* 2MB */
	373	#else
	374	MMU_SECTION_SHIFT = 20, /* 1MB */
	375	#endif
0dde7f53 SG	376	MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
	377	};
	378
a592e6fb	379	#ifdef CONFIG_CPU_V7
97840b5d BB	380	/* TTBR0 bits */
	381	#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
	382	#define TTBR0_RGN_NC (0 << 3)
	383	#define TTBR0_RGN_WBWA (1 << 3)
	384	#define TTBR0_RGN_WT (2 << 3)
	385	#define TTBR0_RGN_WB (3 << 3)
	386	/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
	387	#define TTBR0_IRGN_NC (0 << 0 \| 0 << 6)
	388	#define TTBR0_IRGN_WBWA (0 << 0 \| 1 << 6)
	389	#define TTBR0_IRGN_WT (1 << 0 \| 0 << 6)
	390	#define TTBR0_IRGN_WB (1 << 0 \| 1 << 6)
	391	#endif
	392
0dde7f53 SG	393	/**
	394	* Register an update to the page tables, and flush the TLB
	395	*
	396	* \param start start address of update in page table
	397	* \param stop stop address of update in page table
	398	*/
	399	void mmu_page_table_flush(unsigned long start, unsigned long stop);
	400
677e62f4 JCPV	401	#endif /* __ASSEMBLY__ */
	402
	403	#define arch_align_stack(x) (x)
	404
	405	#endif /* __KERNEL__ */
	406
0ae76531 DF	407	#endif /* CONFIG_ARM64 */
0ae76531 DF	408
dad17fd5 SDPP	409	#ifndef __ASSEMBLY__
	410	/**
	411	* Change the cache settings for a region.
	412	*
	413	* \param start start address of memory region to change
	414	* \param size size of memory region to change
	415	* \param option dcache option to select
	416	*/
	417	void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
	418	enum dcache_option option);
	419
88f965d7 SW	420	#ifdef CONFIG_SYS_NONCACHED_MEMORY
	421	void noncached_init(void);
	422	phys_addr_t noncached_alloc(size_t size, size_t align);
	423	#endif /* CONFIG_SYS_NONCACHED_MEMORY */
	424
dad17fd5 SDPP	425	#endif /* __ASSEMBLY__ */
dad17fd5 SDPP	426
677e62f4	427	#endif