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003b657e MK |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> | |
4 | */ | |
5 | ||
d678a59d | 6 | #include <common.h> |
003b657e | 7 | #include <dm.h> |
a609353e | 8 | #include <dm/uclass-internal.h> |
003b657e | 9 | #include <efi_loader.h> |
8b9c7705 | 10 | #include <lmb.h> |
003b657e MK |
11 | |
12 | #include <asm/armv8/mmu.h> | |
13 | #include <asm/global_data.h> | |
14 | #include <asm/io.h> | |
15 | #include <asm/system.h> | |
16 | ||
17 | DECLARE_GLOBAL_DATA_PTR; | |
18 | ||
e53237aa | 19 | /* Apple M1/M2 */ |
a89fea7f MK |
20 | |
21 | static struct mm_region t8103_mem_map[] = { | |
003b657e MK |
22 | { |
23 | /* I/O */ | |
24 | .virt = 0x200000000, | |
25 | .phys = 0x200000000, | |
a89fea7f MK |
26 | .size = 2UL * SZ_1G, |
27 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
28 | PTE_BLOCK_NON_SHARE | | |
29 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
30 | }, { | |
31 | /* I/O */ | |
32 | .virt = 0x380000000, | |
33 | .phys = 0x380000000, | |
34 | .size = SZ_1G, | |
003b657e MK |
35 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
36 | PTE_BLOCK_NON_SHARE | | |
37 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
38 | }, { | |
39 | /* I/O */ | |
40 | .virt = 0x500000000, | |
41 | .phys = 0x500000000, | |
a89fea7f | 42 | .size = SZ_1G, |
003b657e MK |
43 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
44 | PTE_BLOCK_NON_SHARE | | |
45 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
46 | }, { | |
47 | /* I/O */ | |
48 | .virt = 0x680000000, | |
49 | .phys = 0x680000000, | |
50 | .size = SZ_512M, | |
51 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
52 | PTE_BLOCK_NON_SHARE | | |
53 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
54 | }, { | |
55 | /* PCIE */ | |
56 | .virt = 0x6a0000000, | |
57 | .phys = 0x6a0000000, | |
58 | .size = SZ_512M, | |
59 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
60 | PTE_BLOCK_INNER_SHARE | | |
61 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
62 | }, { | |
63 | /* PCIE */ | |
64 | .virt = 0x6c0000000, | |
65 | .phys = 0x6c0000000, | |
66 | .size = SZ_1G, | |
67 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
68 | PTE_BLOCK_INNER_SHARE | | |
69 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
70 | }, { | |
71 | /* RAM */ | |
72 | .virt = 0x800000000, | |
73 | .phys = 0x800000000, | |
74 | .size = 8UL * SZ_1G, | |
75 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
76 | PTE_BLOCK_INNER_SHARE | |
77 | }, { | |
a89fea7f MK |
78 | /* Framebuffer */ |
79 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | | |
80 | PTE_BLOCK_INNER_SHARE | | |
81 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
82 | }, { | |
83 | /* List terminator */ | |
003b657e | 84 | 0, |
a89fea7f MK |
85 | } |
86 | }; | |
87 | ||
88 | /* Apple M1 Pro/Max */ | |
89 | ||
90 | static struct mm_region t6000_mem_map[] = { | |
91 | { | |
92 | /* I/O */ | |
93 | .virt = 0x280000000, | |
94 | .phys = 0x280000000, | |
95 | .size = SZ_1G, | |
96 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
97 | PTE_BLOCK_NON_SHARE | | |
98 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
99 | }, { | |
100 | /* I/O */ | |
101 | .virt = 0x380000000, | |
102 | .phys = 0x380000000, | |
103 | .size = SZ_1G, | |
104 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
105 | PTE_BLOCK_NON_SHARE | | |
106 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
107 | }, { | |
108 | /* I/O */ | |
109 | .virt = 0x580000000, | |
110 | .phys = 0x580000000, | |
111 | .size = SZ_512M, | |
112 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
113 | PTE_BLOCK_NON_SHARE | | |
114 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
115 | }, { | |
116 | /* PCIE */ | |
117 | .virt = 0x5a0000000, | |
118 | .phys = 0x5a0000000, | |
119 | .size = SZ_512M, | |
120 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
121 | PTE_BLOCK_INNER_SHARE | | |
122 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
123 | }, { | |
124 | /* PCIE */ | |
125 | .virt = 0x5c0000000, | |
126 | .phys = 0x5c0000000, | |
127 | .size = SZ_1G, | |
128 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
129 | PTE_BLOCK_INNER_SHARE | | |
130 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
131 | }, { | |
132 | /* I/O */ | |
133 | .virt = 0x700000000, | |
134 | .phys = 0x700000000, | |
135 | .size = SZ_1G, | |
136 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
137 | PTE_BLOCK_NON_SHARE | | |
138 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
139 | }, { | |
140 | /* I/O */ | |
141 | .virt = 0xb00000000, | |
142 | .phys = 0xb00000000, | |
143 | .size = SZ_1G, | |
144 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
145 | PTE_BLOCK_NON_SHARE | | |
146 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
147 | }, { | |
148 | /* I/O */ | |
149 | .virt = 0xf00000000, | |
150 | .phys = 0xf00000000, | |
151 | .size = SZ_1G, | |
152 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
153 | PTE_BLOCK_NON_SHARE | | |
154 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
155 | }, { | |
156 | /* I/O */ | |
157 | .virt = 0x1300000000, | |
158 | .phys = 0x1300000000, | |
159 | .size = SZ_1G, | |
160 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
161 | PTE_BLOCK_NON_SHARE | | |
162 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
163 | }, { | |
164 | /* RAM */ | |
165 | .virt = 0x10000000000, | |
166 | .phys = 0x10000000000, | |
167 | .size = 16UL * SZ_1G, | |
168 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
169 | PTE_BLOCK_INNER_SHARE | |
170 | }, { | |
171 | /* Framebuffer */ | |
172 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | | |
173 | PTE_BLOCK_INNER_SHARE | | |
174 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
003b657e MK |
175 | }, { |
176 | /* List terminator */ | |
177 | 0, | |
178 | } | |
179 | }; | |
180 | ||
585fc1c8 JG |
181 | /* Apple M1 Ultra */ |
182 | ||
183 | static struct mm_region t6002_mem_map[] = { | |
184 | { | |
185 | /* I/O */ | |
186 | .virt = 0x280000000, | |
187 | .phys = 0x280000000, | |
188 | .size = SZ_1G, | |
189 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
190 | PTE_BLOCK_NON_SHARE | | |
191 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
192 | }, { | |
193 | /* I/O */ | |
194 | .virt = 0x380000000, | |
195 | .phys = 0x380000000, | |
196 | .size = SZ_1G, | |
197 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
198 | PTE_BLOCK_NON_SHARE | | |
199 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
200 | }, { | |
201 | /* I/O */ | |
202 | .virt = 0x580000000, | |
203 | .phys = 0x580000000, | |
204 | .size = SZ_512M, | |
205 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
206 | PTE_BLOCK_NON_SHARE | | |
207 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
208 | }, { | |
209 | /* PCIE */ | |
210 | .virt = 0x5a0000000, | |
211 | .phys = 0x5a0000000, | |
212 | .size = SZ_512M, | |
213 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
214 | PTE_BLOCK_INNER_SHARE | | |
215 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
216 | }, { | |
217 | /* PCIE */ | |
218 | .virt = 0x5c0000000, | |
219 | .phys = 0x5c0000000, | |
220 | .size = SZ_1G, | |
221 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
222 | PTE_BLOCK_INNER_SHARE | | |
223 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
224 | }, { | |
225 | /* I/O */ | |
226 | .virt = 0x700000000, | |
227 | .phys = 0x700000000, | |
228 | .size = SZ_1G, | |
229 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
230 | PTE_BLOCK_NON_SHARE | | |
231 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
232 | }, { | |
233 | /* I/O */ | |
234 | .virt = 0xb00000000, | |
235 | .phys = 0xb00000000, | |
236 | .size = SZ_1G, | |
237 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
238 | PTE_BLOCK_NON_SHARE | | |
239 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
240 | }, { | |
241 | /* I/O */ | |
242 | .virt = 0xf00000000, | |
243 | .phys = 0xf00000000, | |
244 | .size = SZ_1G, | |
245 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
246 | PTE_BLOCK_NON_SHARE | | |
247 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
248 | }, { | |
249 | /* I/O */ | |
250 | .virt = 0x1300000000, | |
251 | .phys = 0x1300000000, | |
252 | .size = SZ_1G, | |
253 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
254 | PTE_BLOCK_NON_SHARE | | |
255 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
256 | }, { | |
257 | /* I/O */ | |
258 | .virt = 0x2280000000, | |
259 | .phys = 0x2280000000, | |
260 | .size = SZ_1G, | |
261 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
262 | PTE_BLOCK_NON_SHARE | | |
263 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
264 | }, { | |
265 | /* I/O */ | |
266 | .virt = 0x2380000000, | |
267 | .phys = 0x2380000000, | |
268 | .size = SZ_1G, | |
269 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
270 | PTE_BLOCK_NON_SHARE | | |
271 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
272 | }, { | |
273 | /* I/O */ | |
274 | .virt = 0x2580000000, | |
275 | .phys = 0x2580000000, | |
276 | .size = SZ_512M, | |
277 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
278 | PTE_BLOCK_NON_SHARE | | |
279 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
280 | }, { | |
281 | /* PCIE */ | |
282 | .virt = 0x25a0000000, | |
283 | .phys = 0x25a0000000, | |
284 | .size = SZ_512M, | |
285 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
286 | PTE_BLOCK_INNER_SHARE | | |
287 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
288 | }, { | |
289 | /* PCIE */ | |
290 | .virt = 0x25c0000000, | |
291 | .phys = 0x25c0000000, | |
292 | .size = SZ_1G, | |
293 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
294 | PTE_BLOCK_INNER_SHARE | | |
295 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
296 | }, { | |
297 | /* I/O */ | |
298 | .virt = 0x2700000000, | |
299 | .phys = 0x2700000000, | |
300 | .size = SZ_1G, | |
301 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
302 | PTE_BLOCK_NON_SHARE | | |
303 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
304 | }, { | |
305 | /* I/O */ | |
306 | .virt = 0x2b00000000, | |
307 | .phys = 0x2b00000000, | |
308 | .size = SZ_1G, | |
309 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
310 | PTE_BLOCK_NON_SHARE | | |
311 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
312 | }, { | |
313 | /* I/O */ | |
314 | .virt = 0x2f00000000, | |
315 | .phys = 0x2f00000000, | |
316 | .size = SZ_1G, | |
317 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
318 | PTE_BLOCK_NON_SHARE | | |
319 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
320 | }, { | |
321 | /* I/O */ | |
322 | .virt = 0x3300000000, | |
323 | .phys = 0x3300000000, | |
324 | .size = SZ_1G, | |
325 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
326 | PTE_BLOCK_NON_SHARE | | |
327 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
328 | }, { | |
329 | /* RAM */ | |
330 | .virt = 0x10000000000, | |
331 | .phys = 0x10000000000, | |
332 | .size = 16UL * SZ_1G, | |
333 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
334 | PTE_BLOCK_INNER_SHARE | |
335 | }, { | |
336 | /* Framebuffer */ | |
337 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | | |
338 | PTE_BLOCK_INNER_SHARE | | |
339 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
340 | }, { | |
341 | /* List terminator */ | |
342 | 0, | |
343 | } | |
344 | }; | |
345 | ||
4a97874d MK |
346 | /* Apple M2 Pro/Max */ |
347 | ||
348 | static struct mm_region t6020_mem_map[] = { | |
349 | { | |
350 | /* I/O */ | |
351 | .virt = 0x280000000, | |
352 | .phys = 0x280000000, | |
353 | .size = SZ_1G, | |
354 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
355 | PTE_BLOCK_NON_SHARE | | |
356 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
357 | }, { | |
358 | /* I/O */ | |
359 | .virt = 0x340000000, | |
360 | .phys = 0x340000000, | |
361 | .size = SZ_1G, | |
362 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
363 | PTE_BLOCK_NON_SHARE | | |
364 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
365 | }, { | |
366 | /* I/O */ | |
367 | .virt = 0x380000000, | |
368 | .phys = 0x380000000, | |
369 | .size = SZ_1G, | |
370 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
371 | PTE_BLOCK_NON_SHARE | | |
372 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
6bfd07bf JG |
373 | }, { |
374 | /* I/O */ | |
375 | .virt = 0x400000000, | |
376 | .phys = 0x400000000, | |
377 | .size = SZ_1G, | |
378 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
379 | PTE_BLOCK_NON_SHARE | | |
380 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
381 | }, { | |
382 | /* I/O */ | |
383 | .virt = 0x480000000, | |
384 | .phys = 0x480000000, | |
385 | .size = SZ_1G, | |
386 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
387 | PTE_BLOCK_NON_SHARE | | |
388 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
4a97874d MK |
389 | }, { |
390 | /* I/O */ | |
391 | .virt = 0x580000000, | |
392 | .phys = 0x580000000, | |
393 | .size = SZ_512M, | |
394 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
395 | PTE_BLOCK_NON_SHARE | | |
396 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
397 | }, { | |
398 | /* PCIE */ | |
399 | .virt = 0x5a0000000, | |
400 | .phys = 0x5a0000000, | |
401 | .size = SZ_512M, | |
402 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
403 | PTE_BLOCK_INNER_SHARE | | |
404 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
405 | }, { | |
406 | /* PCIE */ | |
407 | .virt = 0x5c0000000, | |
408 | .phys = 0x5c0000000, | |
409 | .size = SZ_1G, | |
410 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
411 | PTE_BLOCK_INNER_SHARE | | |
412 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
413 | }, { | |
414 | /* I/O */ | |
415 | .virt = 0x700000000, | |
416 | .phys = 0x700000000, | |
417 | .size = SZ_1G, | |
418 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
419 | PTE_BLOCK_NON_SHARE | | |
420 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
421 | }, { | |
422 | /* I/O */ | |
423 | .virt = 0xb00000000, | |
424 | .phys = 0xb00000000, | |
425 | .size = SZ_1G, | |
426 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
427 | PTE_BLOCK_NON_SHARE | | |
428 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
429 | }, { | |
430 | /* I/O */ | |
431 | .virt = 0xf00000000, | |
432 | .phys = 0xf00000000, | |
433 | .size = SZ_1G, | |
434 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
435 | PTE_BLOCK_NON_SHARE | | |
436 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
437 | }, { | |
438 | /* I/O */ | |
439 | .virt = 0x1300000000, | |
440 | .phys = 0x1300000000, | |
441 | .size = SZ_1G, | |
442 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
443 | PTE_BLOCK_NON_SHARE | | |
444 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
445 | }, { | |
446 | /* RAM */ | |
447 | .virt = 0x10000000000, | |
448 | .phys = 0x10000000000, | |
449 | .size = 16UL * SZ_1G, | |
450 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
451 | PTE_BLOCK_INNER_SHARE | |
452 | }, { | |
453 | /* Framebuffer */ | |
454 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | | |
455 | PTE_BLOCK_INNER_SHARE | | |
456 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
457 | }, { | |
458 | /* List terminator */ | |
459 | 0, | |
460 | } | |
461 | }; | |
462 | ||
0f2f5191 JG |
463 | /* Apple M2 Ultra */ |
464 | ||
465 | static struct mm_region t6022_mem_map[] = { | |
466 | { | |
467 | /* I/O */ | |
468 | .virt = 0x280000000, | |
469 | .phys = 0x280000000, | |
470 | .size = SZ_1G, | |
471 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
472 | PTE_BLOCK_NON_SHARE | | |
473 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
474 | }, { | |
475 | /* I/O */ | |
476 | .virt = 0x340000000, | |
477 | .phys = 0x340000000, | |
478 | .size = SZ_1G, | |
479 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
480 | PTE_BLOCK_NON_SHARE | | |
481 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
482 | }, { | |
483 | /* I/O */ | |
484 | .virt = 0x380000000, | |
485 | .phys = 0x380000000, | |
486 | .size = SZ_1G, | |
487 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
488 | PTE_BLOCK_NON_SHARE | | |
489 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
6bfd07bf JG |
490 | }, { |
491 | /* I/O */ | |
492 | .virt = 0x400000000, | |
493 | .phys = 0x400000000, | |
494 | .size = SZ_1G, | |
495 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
496 | PTE_BLOCK_NON_SHARE | | |
497 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
498 | }, { | |
499 | /* I/O */ | |
500 | .virt = 0x480000000, | |
501 | .phys = 0x480000000, | |
502 | .size = SZ_1G, | |
503 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
504 | PTE_BLOCK_NON_SHARE | | |
505 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
0f2f5191 JG |
506 | }, { |
507 | /* I/O */ | |
508 | .virt = 0x580000000, | |
509 | .phys = 0x580000000, | |
510 | .size = SZ_512M, | |
511 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
512 | PTE_BLOCK_NON_SHARE | | |
513 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
514 | }, { | |
515 | /* PCIE */ | |
516 | .virt = 0x5a0000000, | |
517 | .phys = 0x5a0000000, | |
518 | .size = SZ_512M, | |
519 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
520 | PTE_BLOCK_INNER_SHARE | | |
521 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
522 | }, { | |
523 | /* PCIE */ | |
524 | .virt = 0x5c0000000, | |
525 | .phys = 0x5c0000000, | |
526 | .size = SZ_1G, | |
527 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
528 | PTE_BLOCK_INNER_SHARE | | |
529 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
530 | }, { | |
531 | /* I/O */ | |
532 | .virt = 0x700000000, | |
533 | .phys = 0x700000000, | |
534 | .size = SZ_1G, | |
535 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
536 | PTE_BLOCK_NON_SHARE | | |
537 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
538 | }, { | |
539 | /* I/O */ | |
540 | .virt = 0xb00000000, | |
541 | .phys = 0xb00000000, | |
542 | .size = SZ_1G, | |
543 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
544 | PTE_BLOCK_NON_SHARE | | |
545 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
546 | }, { | |
547 | /* I/O */ | |
548 | .virt = 0xf00000000, | |
549 | .phys = 0xf00000000, | |
550 | .size = SZ_1G, | |
551 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
552 | PTE_BLOCK_NON_SHARE | | |
553 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
554 | }, { | |
555 | /* I/O */ | |
556 | .virt = 0x1300000000, | |
557 | .phys = 0x1300000000, | |
558 | .size = SZ_1G, | |
559 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
560 | PTE_BLOCK_NON_SHARE | | |
561 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
562 | }, { | |
563 | /* I/O */ | |
564 | .virt = 0x2280000000, | |
565 | .phys = 0x2280000000, | |
566 | .size = SZ_1G, | |
567 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
568 | PTE_BLOCK_NON_SHARE | | |
569 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
570 | }, { | |
571 | /* I/O */ | |
572 | .virt = 0x2340000000, | |
573 | .phys = 0x2340000000, | |
574 | .size = SZ_1G, | |
575 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
576 | PTE_BLOCK_NON_SHARE | | |
577 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
578 | }, { | |
579 | /* I/O */ | |
580 | .virt = 0x2380000000, | |
581 | .phys = 0x2380000000, | |
582 | .size = SZ_1G, | |
583 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
584 | PTE_BLOCK_NON_SHARE | | |
585 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
6bfd07bf JG |
586 | }, { |
587 | /* I/O */ | |
588 | .virt = 0x2400000000, | |
589 | .phys = 0x2400000000, | |
590 | .size = SZ_1G, | |
591 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
592 | PTE_BLOCK_NON_SHARE | | |
593 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
594 | }, { | |
595 | /* I/O */ | |
596 | .virt = 0x2480000000, | |
597 | .phys = 0x2480000000, | |
598 | .size = SZ_1G, | |
599 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
600 | PTE_BLOCK_NON_SHARE | | |
601 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
0f2f5191 JG |
602 | }, { |
603 | /* I/O */ | |
604 | .virt = 0x2580000000, | |
605 | .phys = 0x2580000000, | |
606 | .size = SZ_512M, | |
607 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
608 | PTE_BLOCK_NON_SHARE | | |
609 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
610 | }, { | |
611 | /* PCIE */ | |
612 | .virt = 0x25a0000000, | |
613 | .phys = 0x25a0000000, | |
614 | .size = SZ_512M, | |
615 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
616 | PTE_BLOCK_INNER_SHARE | | |
617 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
618 | }, { | |
619 | /* PCIE */ | |
620 | .virt = 0x25c0000000, | |
621 | .phys = 0x25c0000000, | |
622 | .size = SZ_1G, | |
623 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | | |
624 | PTE_BLOCK_INNER_SHARE | | |
625 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
626 | }, { | |
627 | /* I/O */ | |
628 | .virt = 0x2700000000, | |
629 | .phys = 0x2700000000, | |
630 | .size = SZ_1G, | |
631 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
632 | PTE_BLOCK_NON_SHARE | | |
633 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
634 | }, { | |
635 | /* I/O */ | |
636 | .virt = 0x2b00000000, | |
637 | .phys = 0x2b00000000, | |
638 | .size = SZ_1G, | |
639 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
640 | PTE_BLOCK_NON_SHARE | | |
641 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
642 | }, { | |
643 | /* I/O */ | |
644 | .virt = 0x2f00000000, | |
645 | .phys = 0x2f00000000, | |
646 | .size = SZ_1G, | |
647 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
648 | PTE_BLOCK_NON_SHARE | | |
649 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
650 | }, { | |
651 | /* I/O */ | |
652 | .virt = 0x3300000000, | |
653 | .phys = 0x3300000000, | |
654 | .size = SZ_1G, | |
655 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
656 | PTE_BLOCK_NON_SHARE | | |
657 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
658 | }, { | |
659 | /* RAM */ | |
660 | .virt = 0x10000000000, | |
661 | .phys = 0x10000000000, | |
662 | .size = 16UL * SZ_1G, | |
663 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
664 | PTE_BLOCK_INNER_SHARE | |
665 | }, { | |
666 | /* Framebuffer */ | |
667 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | | |
668 | PTE_BLOCK_INNER_SHARE | | |
669 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
670 | }, { | |
671 | /* List terminator */ | |
672 | 0, | |
673 | } | |
674 | }; | |
675 | ||
a89fea7f | 676 | struct mm_region *mem_map; |
003b657e MK |
677 | |
678 | int board_init(void) | |
679 | { | |
680 | return 0; | |
681 | } | |
682 | ||
683 | int dram_init(void) | |
a89fea7f MK |
684 | { |
685 | return fdtdec_setup_mem_size_base(); | |
686 | } | |
687 | ||
688 | int dram_init_banksize(void) | |
689 | { | |
690 | return fdtdec_setup_memory_banksize(); | |
691 | } | |
692 | ||
693 | extern long fw_dtb_pointer; | |
694 | ||
695 | void *board_fdt_blob_setup(int *err) | |
696 | { | |
697 | /* Return DTB pointer passed by m1n1 */ | |
698 | *err = 0; | |
699 | return (void *)fw_dtb_pointer; | |
700 | } | |
701 | ||
702 | void build_mem_map(void) | |
003b657e MK |
703 | { |
704 | ofnode node; | |
003b657e MK |
705 | fdt_addr_t base; |
706 | fdt_size_t size; | |
a89fea7f MK |
707 | int i; |
708 | ||
e53237aa JG |
709 | if (of_machine_is_compatible("apple,t8103") || |
710 | of_machine_is_compatible("apple,t8112")) | |
a89fea7f | 711 | mem_map = t8103_mem_map; |
4a97874d MK |
712 | else if (of_machine_is_compatible("apple,t6000") || |
713 | of_machine_is_compatible("apple,t6001")) | |
a89fea7f | 714 | mem_map = t6000_mem_map; |
585fc1c8 JG |
715 | else if (of_machine_is_compatible("apple,t6002")) |
716 | mem_map = t6002_mem_map; | |
4a97874d MK |
717 | else if (of_machine_is_compatible("apple,t6020") || |
718 | of_machine_is_compatible("apple,t6021")) | |
719 | mem_map = t6020_mem_map; | |
0f2f5191 JG |
720 | else if (of_machine_is_compatible("apple,t6022")) |
721 | mem_map = t6022_mem_map; | |
a89fea7f MK |
722 | else |
723 | panic("Unsupported SoC\n"); | |
003b657e | 724 | |
a89fea7f MK |
725 | /* Find list terminator. */ |
726 | for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) | |
727 | ; | |
728 | ||
729 | /* Align RAM mapping to page boundaries */ | |
730 | base = gd->bd->bi_dram[0].start; | |
731 | size = gd->bd->bi_dram[0].size; | |
732 | size += (base - ALIGN_DOWN(base, SZ_4K)); | |
733 | base = ALIGN_DOWN(base, SZ_4K); | |
734 | size = ALIGN(size, SZ_4K); | |
003b657e MK |
735 | |
736 | /* Update RAM mapping */ | |
a89fea7f MK |
737 | mem_map[i - 2].virt = base; |
738 | mem_map[i - 2].phys = base; | |
739 | mem_map[i - 2].size = size; | |
003b657e MK |
740 | |
741 | node = ofnode_path("/chosen/framebuffer"); | |
742 | if (!ofnode_valid(node)) | |
a89fea7f | 743 | return; |
003b657e MK |
744 | |
745 | base = ofnode_get_addr_size(node, "reg", &size); | |
746 | if (base == FDT_ADDR_T_NONE) | |
a89fea7f | 747 | return; |
003b657e | 748 | |
a89fea7f MK |
749 | /* Align framebuffer mapping to page boundaries */ |
750 | size += (base - ALIGN_DOWN(base, SZ_4K)); | |
751 | base = ALIGN_DOWN(base, SZ_4K); | |
752 | size = ALIGN(size, SZ_4K); | |
003b657e | 753 | |
a89fea7f MK |
754 | /* Add framebuffer mapping */ |
755 | mem_map[i - 1].virt = base; | |
756 | mem_map[i - 1].phys = base; | |
757 | mem_map[i - 1].size = size; | |
003b657e MK |
758 | } |
759 | ||
a89fea7f | 760 | void enable_caches(void) |
003b657e | 761 | { |
a89fea7f | 762 | build_mem_map(); |
003b657e | 763 | |
a89fea7f MK |
764 | icache_enable(); |
765 | dcache_enable(); | |
003b657e MK |
766 | } |
767 | ||
a89fea7f | 768 | u64 get_page_table_size(void) |
003b657e | 769 | { |
a89fea7f | 770 | return SZ_256K; |
003b657e | 771 | } |
6fb4f738 | 772 | |
8b9c7705 MK |
773 | #define KERNEL_COMP_SIZE SZ_128M |
774 | ||
6fb4f738 JG |
775 | int board_late_init(void) |
776 | { | |
8b9c7705 | 777 | struct lmb lmb; |
6fb4f738 JG |
778 | u32 status = 0; |
779 | ||
8b9c7705 | 780 | lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); |
6fb4f738 JG |
781 | |
782 | /* somewhat based on the Linux Kernel boot requirements: | |
783 | * align by 2M and maximal FDT size 2M | |
784 | */ | |
8b9c7705 MK |
785 | status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M)); |
786 | status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M)); | |
787 | status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M)); | |
788 | status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M)); | |
789 | status |= env_set_hex("kernel_comp_addr_r", | |
790 | lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M)); | |
791 | status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); | |
792 | status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M)); | |
793 | status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M)); | |
6fb4f738 JG |
794 | |
795 | if (status) | |
796 | log_warning("late_init: Failed to set run time variables\n"); | |
797 | ||
798 | return 0; | |
799 | } | |
a609353e MK |
800 | |
801 | int ft_board_setup(void *blob, struct bd_info *bd) | |
802 | { | |
803 | struct udevice *dev; | |
804 | const char *stdoutname; | |
805 | int node, ret; | |
806 | ||
807 | /* | |
808 | * Modify the "stdout-path" property under "/chosen" to point | |
809 | * at "/chosen/framebuffer if a keyboard is available and | |
810 | * we're not running under the m1n1 hypervisor. | |
811 | * Developers can override this behaviour by dropping | |
812 | * "vidconsole" from the "stdout" environment variable. | |
813 | */ | |
814 | ||
815 | /* EL1 means we're running under the m1n1 hypervisor. */ | |
816 | if (current_el() == 1) | |
817 | return 0; | |
818 | ||
819 | ret = uclass_find_device(UCLASS_KEYBOARD, 0, &dev); | |
820 | if (ret < 0) | |
821 | return 0; | |
822 | ||
823 | stdoutname = env_get("stdout"); | |
824 | if (!stdoutname || !strstr(stdoutname, "vidconsole")) | |
825 | return 0; | |
826 | ||
827 | /* Make sure we actually have a framebuffer. */ | |
828 | node = fdt_path_offset(blob, "/chosen/framebuffer"); | |
829 | if (node < 0 || !fdtdec_get_is_enabled(blob, node)) | |
830 | return 0; | |
831 | ||
832 | node = fdt_path_offset(blob, "/chosen"); | |
833 | if (node < 0) | |
834 | return 0; | |
835 | fdt_setprop_string(blob, node, "stdout-path", "/chosen/framebuffer"); | |
836 | ||
837 | return 0; | |
838 | } |