[thirdparty/u-boot.git] / arch / arm / mach-at91 / arm926ejs / at91sam9261_devices.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>

/*
 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
 * peripheral pins. Good to have if hardware is soldered optionally
 * or in case of SPI no slave is selected. Avoid lines to float
 * needlessly. Use a short local PUP define.
 *
 * Due to errata "TXD floats when CTS is inactive" pullups are always
 * on for TXD pins.
 */
#ifdef CONFIG_AT91_GPIO_PULLUP
# define PUP CONFIG_AT91_GPIO_PULLUP
#else
# define PUP 0
#endif

void at91_serial0_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 8, 1);		/* TXD0 */
	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);		/* RXD0 */
	at91_periph_clk_enable(ATMEL_ID_USART0);
}

void at91_serial1_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 12, 1);		/* TXD1 */
	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);		/* RXD1 */
	at91_periph_clk_enable(ATMEL_ID_USART1);
}

void at91_serial2_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 14, 1);		/* TXD2 */
	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);		/* RXD2 */
	at91_periph_clk_enable(ATMEL_ID_USART2);
}

void at91_seriald_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTA, 9, 0);		/* DRXD */
	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);		/* DTXD */
	at91_periph_clk_enable(ATMEL_ID_SYS);
}

#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */

	at91_periph_clk_enable(ATMEL_ID_SPI0);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
	}
}

void at91_spi1_hw_init(unsigned long cs_mask)
{
	at91_set_a_periph(AT91_PIO_PORTB, 30, PUP);	/* SPI1_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 31, PUP);	/* SPI1_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 29, PUP);	/* SPI1_SPCK */

	at91_periph_clk_enable(ATMEL_ID_SPI1);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
	}
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7ebafb7e JCPV	2	/*
7ebafb7e JCPV	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <stelian@popies.net>
7ebafb7e	5	* Lead Tech Design <www.leadtechdesign.com>
7ebafb7e JCPV	6	*/
7ebafb7e JCPV	7
d678a59d	8	#include <common.h>
3ad24802	9	#include <asm/io.h>
7ebafb7e	10	#include <asm/arch/at91_common.h>
eced5a7e	11	#include <asm/arch/clk.h>
7ebafb7e	12	#include <asm/arch/gpio.h>
3ad24802 AD	13
	14	/*
	15	* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
	16	* peripheral pins. Good to have if hardware is soldered optionally
	17	* or in case of SPI no slave is selected. Avoid lines to float
	18	* needlessly. Use a short local PUP define.
	19	*
	20	* Due to errata "TXD floats when CTS is inactive" pullups are always
	21	* on for TXD pins.
	22	*/
	23	#ifdef CONFIG_AT91_GPIO_PULLUP
	24	# define PUP CONFIG_AT91_GPIO_PULLUP
	25	#else
	26	# define PUP 0
	27	#endif
7ebafb7e	28
1699da62 JCPV	29	void at91_serial0_hw_init(void)
1699da62 JCPV	30	{
7f9e8633 JS	31	at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
7f9e8633 JS	32	at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
eced5a7e	33	at91_periph_clk_enable(ATMEL_ID_USART0);
1699da62 JCPV	34	}
	35
	36	void at91_serial1_hw_init(void)
	37	{
7f9e8633 JS	38	at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
7f9e8633 JS	39	at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
eced5a7e	40	at91_periph_clk_enable(ATMEL_ID_USART1);
1699da62 JCPV	41	}
	42
	43	void at91_serial2_hw_init(void)
	44	{
7f9e8633 JS	45	at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
7f9e8633 JS	46	at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
eced5a7e	47	at91_periph_clk_enable(ATMEL_ID_USART2);
1699da62 JCPV	48	}
1699da62 JCPV	49
3ad24802	50	void at91_seriald_hw_init(void)
1699da62	51	{
7f9e8633 JS	52	at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
7f9e8633 JS	53	at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
eced5a7e	54	at91_periph_clk_enable(ATMEL_ID_SYS);
1699da62 JCPV	55	}
1699da62 JCPV	56
c68c03f5	57	#ifdef CONFIG_ATMEL_SPI
7ebafb7e JCPV	58	void at91_spi0_hw_init(unsigned long cs_mask)
7ebafb7e JCPV	59	{
3ad24802 AD	60	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
	61	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
	62	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
7ebafb7e	63
eced5a7e	64	at91_periph_clk_enable(ATMEL_ID_SPI0);
7ebafb7e JCPV	65
7ebafb7e JCPV	66	if (cs_mask & (1 << 0)) {
7f9e8633	67	at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
7ebafb7e JCPV	68	}
7ebafb7e JCPV	69	if (cs_mask & (1 << 1)) {
7f9e8633	70	at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
7ebafb7e JCPV	71	}
7ebafb7e JCPV	72	if (cs_mask & (1 << 2)) {
7f9e8633	73	at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
7ebafb7e JCPV	74	}
7ebafb7e JCPV	75	if (cs_mask & (1 << 3)) {
7f9e8633	76	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
a47492ac JCPV	77	}
a47492ac JCPV	78	if (cs_mask & (1 << 4)) {
7f9e8633	79	at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
a47492ac JCPV	80	}
a47492ac JCPV	81	if (cs_mask & (1 << 5)) {
7f9e8633	82	at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
a47492ac JCPV	83	}
a47492ac JCPV	84	if (cs_mask & (1 << 6)) {
7f9e8633	85	at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
a47492ac JCPV	86	}
a47492ac JCPV	87	if (cs_mask & (1 << 7)) {
7f9e8633	88	at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
7ebafb7e JCPV	89	}
	90	}
	91
	92	void at91_spi1_hw_init(unsigned long cs_mask)
	93	{
3ad24802 AD	94	at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */
	95	at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */
	96	at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */
7ebafb7e	97
eced5a7e	98	at91_periph_clk_enable(ATMEL_ID_SPI1);
7ebafb7e JCPV	99
7ebafb7e JCPV	100	if (cs_mask & (1 << 0)) {
7f9e8633	101	at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
7ebafb7e JCPV	102	}
7ebafb7e JCPV	103	if (cs_mask & (1 << 1)) {
7f9e8633	104	at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
7ebafb7e JCPV	105	}
7ebafb7e JCPV	106	if (cs_mask & (1 << 2)) {
7f9e8633	107	at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
7ebafb7e JCPV	108	}
7ebafb7e JCPV	109	if (cs_mask & (1 << 3)) {
7f9e8633	110	at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
a47492ac JCPV	111	}
a47492ac JCPV	112	if (cs_mask & (1 << 4)) {
7f9e8633	113	at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
a47492ac JCPV	114	}
a47492ac JCPV	115	if (cs_mask & (1 << 5)) {
7f9e8633	116	at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
a47492ac JCPV	117	}
a47492ac JCPV	118	if (cs_mask & (1 << 6)) {
7f9e8633	119	at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
a47492ac JCPV	120	}
a47492ac JCPV	121	if (cs_mask & (1 << 7)) {
7f9e8633	122	at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
7ebafb7e JCPV	123	}
7ebafb7e JCPV	124	}
1699da62	125	#endif