[thirdparty/u-boot.git] / arch / arm / mach-at91 / arm926ejs / timer.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 */

#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pit.h>
#include <asm/arch/clk.h>
#include <div64.h>

#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif

DECLARE_GLOBAL_DATA_PTR;

/*
 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
 * setting the 20 bit counter period to its maximum (0xfffff).
 * (See the relevant data sheets to understand that this really works)
 *
 * We do also mimic the typical powerpc way of incrementing
 * two 32 bit registers called tbl and tbu.
 *
 * Those registers increment at 1/16 the main clock rate.
 */

#define TIMER_LOAD_VAL	0xfffff

/*
 * Use the PITC in full 32 bit incrementing mode
 */
int timer_init(void)
{
	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;

	at91_periph_clk_enable(ATMEL_ID_SYS);

	/* Enable PITC */
	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;

	return 0;
}

/*
 * Return the number of timer ticks per second.
 */
ulong get_tbclk(void)
{
	return gd->arch.timer_rate_hz;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
fefb6c10 SP	2	/*
fefb6c10 SP	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <stelian@popies.net>
fefb6c10	5	* Lead Tech Design <www.leadtechdesign.com>
fefb6c10 SP	6	*/
fefb6c10 SP	7
d678a59d	8	#include <common.h>
691d719d	9	#include <init.h>
049f8d6f	10	#include <time.h>
401d1c4f	11	#include <asm/global_data.h>
86592f60	12	#include <asm/io.h>
fefb6c10	13	#include <asm/arch/hardware.h>
983c1db0	14	#include <asm/arch/at91_pit.h>
6ebff365	15	#include <asm/arch/clk.h>
6ebff365	16	#include <div64.h>
fefb6c10	17
5dca710a RM	18	#if !defined(CONFIG_AT91FAMILY)
	19	# error You need to define CONFIG_AT91FAMILY in your board config!
	20	#endif
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
fefb6c10	24	/*
a8a78f2d	25	* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
fefb6c10	26	* setting the 20 bit counter period to its maximum (0xfffff).
5dca710a RM	27	* (See the relevant data sheets to understand that this really works)
	28	*
	29	* We do also mimic the typical powerpc way of incrementing
	30	* two 32 bit registers called tbl and tbu.
	31	*
	32	* Those registers increment at 1/16 the main clock rate.
fefb6c10	33	*/
fefb6c10	34
5dca710a	35	#define TIMER_LOAD_VAL 0xfffff
6ebff365	36
5dca710a RM	37	/*
	38	* Use the PITC in full 32 bit incrementing mode
	39	*/
61106a56	40	int timer_init(void)
fefb6c10	41	{
9f3fe90f	42	at91_pit_t pit = (at91_pit_t ) ATMEL_BASE_PIT;
5dca710a	43
eced5a7e	44	at91_periph_clk_enable(ATMEL_ID_SYS);
fefb6c10 SP	45
fefb6c10 SP	46	/* Enable PITC */
0cf0b931	47	writel(TIMER_LOAD_VAL \| AT91_PIT_MR_EN , &pit->mr);
fefb6c10	48
b339051c	49	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
6ebff365	50
fefb6c10 SP	51	return 0;
	52	}
	53
fefb6c10	54	/*
5dca710a	55	* Return the number of timer ticks per second.
fefb6c10 SP	56	*/
	57	ulong get_tbclk(void)
	58	{
b339051c	59	return gd->arch.timer_rate_hz;
fefb6c10	60	}