[thirdparty/u-boot.git] / arch / arm / mach-at91 / armv7 / timer.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * (C) Copyright 2013
 * Bo Shen <voice.shen@atmel.com>
 */

#include <common.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pit.h>
#include <asm/arch/clk.h>
#include <div64.h>

#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif

DECLARE_GLOBAL_DATA_PTR;

/*
 * We're using the SAMA5D3x PITC in 32 bit mode, by
 * setting the 20 bit counter period to its maximum (0xfffff).
 * (See the relevant data sheets to understand that this really works)
 *
 * We do also mimic the typical powerpc way of incrementing
 * two 32 bit registers called tbl and tbu.
 *
 * Those registers increment at 1/16 the main clock rate.
 */

#define TIMER_LOAD_VAL	0xfffff

/*
 * Use the PITC in full 32 bit incrementing mode
 */
int timer_init(void)
{
	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;

	/* Enable PITC Clock */
	at91_periph_clk_enable(ATMEL_ID_PIT);

	/* Enable PITC */
	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

	gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;

	return 0;
}

/*
 * Return the number of timer ticks per second.
 */
ulong get_tbclk(void)
{
	return gd->arch.timer_rate_hz;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
3225f34e BS	2	/*
	3	* (C) Copyright 2007-2008
	4	* Stelian Pop <stelian@popies.net>
	5	* Lead Tech Design <www.leadtechdesign.com>
	6	*
	7	* (C) Copyright 2013
	8	* Bo Shen <voice.shen@atmel.com>
3225f34e BS	9	*/
3225f34e BS	10
d678a59d	11	#include <common.h>
691d719d	12	#include <init.h>
049f8d6f	13	#include <time.h>
401d1c4f	14	#include <asm/global_data.h>
3225f34e BS	15	#include <asm/io.h>
	16	#include <asm/arch/hardware.h>
	17	#include <asm/arch/at91_pit.h>
3225f34e BS	18	#include <asm/arch/clk.h>
	19	#include <div64.h>
	20
	21	#if !defined(CONFIG_AT91FAMILY)
	22	# error You need to define CONFIG_AT91FAMILY in your board config!
	23	#endif
	24
	25	DECLARE_GLOBAL_DATA_PTR;
	26
	27	/*
	28	* We're using the SAMA5D3x PITC in 32 bit mode, by
	29	* setting the 20 bit counter period to its maximum (0xfffff).
	30	* (See the relevant data sheets to understand that this really works)
	31	*
	32	* We do also mimic the typical powerpc way of incrementing
	33	* two 32 bit registers called tbl and tbu.
	34	*
	35	* Those registers increment at 1/16 the main clock rate.
	36	*/
	37
	38	#define TIMER_LOAD_VAL 0xfffff
	39
3225f34e BS	40	/*
	41	* Use the PITC in full 32 bit incrementing mode
	42	*/
	43	int timer_init(void)
	44	{
	45	at91_pit_t pit = (at91_pit_t )ATMEL_BASE_PIT;
	46
	47	/* Enable PITC Clock */
184c551b	48	at91_periph_clk_enable(ATMEL_ID_PIT);
3225f34e BS	49
	50	/* Enable PITC */
	51	writel(TIMER_LOAD_VAL \| AT91_PIT_MR_EN , &pit->mr);
	52
927b901b BS	53	gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
927b901b BS	54
3225f34e BS	55	return 0;
	56	}
	57
3225f34e BS	58	/*
	59	* Return the number of timer ticks per second.
	60	*/
	61	ulong get_tbclk(void)
	62	{
	63	return gd->arch.timer_rate_hz;
	64	}