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177e8a5a | 1 | /* |
9606b3c8 | 2 | * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] |
177e8a5a SP |
3 | * |
4 | * Copyright (C) 2005 HP Labs | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
177e8a5a SP |
7 | */ |
8 | ||
9 | #ifndef __ASM_ARCH_AT91_GPIO_H | |
10 | #define __ASM_ARCH_AT91_GPIO_H | |
11 | ||
12 | #include <asm/io.h> | |
1221ce45 | 13 | #include <linux/errno.h> |
177e8a5a | 14 | #include <asm/arch/at91_pio.h> |
23bb28f0 | 15 | #include <asm/arch/hardware.h> |
177e8a5a | 16 | |
83f1072e | 17 | #ifdef CONFIG_ATMEL_LEGACY |
5d8e359c | 18 | |
934e3b52 | 19 | #define PIN_BASE 0 |
177e8a5a SP |
20 | |
21 | #define MAX_GPIO_BANKS 5 | |
22 | ||
23 | /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ | |
24 | ||
25 | #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) | |
26 | #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) | |
27 | #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) | |
28 | #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) | |
29 | #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) | |
30 | #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) | |
31 | #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) | |
32 | #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) | |
33 | #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) | |
34 | #define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) | |
35 | #define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) | |
36 | #define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) | |
37 | #define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) | |
38 | #define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) | |
39 | #define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) | |
40 | #define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) | |
41 | #define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) | |
42 | #define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) | |
43 | #define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) | |
44 | #define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) | |
45 | #define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) | |
46 | #define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) | |
47 | #define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) | |
48 | #define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) | |
49 | #define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) | |
50 | #define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) | |
51 | #define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) | |
52 | #define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) | |
53 | #define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) | |
54 | #define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) | |
55 | #define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) | |
56 | #define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) | |
57 | ||
58 | #define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) | |
59 | #define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) | |
60 | #define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) | |
61 | #define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) | |
62 | #define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) | |
63 | #define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) | |
64 | #define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) | |
65 | #define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) | |
66 | #define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) | |
67 | #define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) | |
68 | #define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) | |
69 | #define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) | |
70 | #define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) | |
71 | #define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) | |
72 | #define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) | |
73 | #define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) | |
74 | #define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) | |
75 | #define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) | |
76 | #define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) | |
77 | #define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) | |
78 | #define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) | |
79 | #define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) | |
80 | #define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) | |
81 | #define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) | |
82 | #define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) | |
83 | #define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) | |
84 | #define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) | |
85 | #define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) | |
86 | #define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) | |
87 | #define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) | |
88 | #define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) | |
89 | #define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) | |
90 | ||
91 | #define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) | |
92 | #define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) | |
93 | #define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) | |
94 | #define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) | |
95 | #define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) | |
96 | #define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) | |
97 | #define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) | |
98 | #define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) | |
99 | #define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) | |
100 | #define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) | |
101 | #define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) | |
102 | #define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) | |
103 | #define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) | |
104 | #define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) | |
105 | #define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) | |
106 | #define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) | |
107 | #define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) | |
108 | #define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) | |
109 | #define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) | |
110 | #define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) | |
111 | #define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) | |
112 | #define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) | |
113 | #define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) | |
114 | #define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) | |
115 | #define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) | |
116 | #define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) | |
117 | #define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) | |
118 | #define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) | |
119 | #define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) | |
120 | #define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) | |
121 | #define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) | |
122 | #define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) | |
123 | ||
124 | #define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) | |
125 | #define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) | |
126 | #define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) | |
127 | #define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) | |
128 | #define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) | |
129 | #define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) | |
130 | #define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) | |
131 | #define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) | |
132 | #define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) | |
133 | #define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) | |
134 | #define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) | |
135 | #define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) | |
136 | #define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) | |
137 | #define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) | |
138 | #define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) | |
139 | #define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) | |
140 | #define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) | |
141 | #define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) | |
142 | #define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) | |
143 | #define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) | |
144 | #define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) | |
145 | #define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) | |
146 | #define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) | |
147 | #define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) | |
148 | #define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) | |
149 | #define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) | |
150 | #define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) | |
151 | #define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) | |
152 | #define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) | |
153 | #define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) | |
154 | #define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) | |
155 | #define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) | |
156 | ||
157 | #define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) | |
158 | #define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) | |
159 | #define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) | |
160 | #define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) | |
161 | #define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) | |
162 | #define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) | |
163 | #define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) | |
164 | #define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) | |
165 | #define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) | |
166 | #define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) | |
167 | #define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) | |
168 | #define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) | |
169 | #define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) | |
170 | #define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) | |
171 | #define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) | |
172 | #define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) | |
173 | #define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) | |
174 | #define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) | |
175 | #define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) | |
176 | #define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) | |
177 | #define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) | |
178 | #define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) | |
179 | #define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) | |
180 | #define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) | |
181 | #define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) | |
182 | #define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) | |
183 | #define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) | |
184 | #define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) | |
185 | #define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) | |
186 | #define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) | |
187 | #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) | |
188 | #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) | |
189 | ||
190 | static unsigned long at91_pios[] = { | |
83f1072e RM |
191 | ATMEL_BASE_PIOA, |
192 | ATMEL_BASE_PIOB, | |
193 | ATMEL_BASE_PIOC, | |
194 | #ifdef ATMEL_BASE_PIOD | |
195 | ATMEL_BASE_PIOD, | |
196 | #ifdef ATMEL_BASE_PIOE | |
197 | ATMEL_BASE_PIOE | |
177e8a5a SP |
198 | #endif |
199 | #endif | |
200 | }; | |
201 | ||
177e8a5a SP |
202 | static inline void *pin_to_controller(unsigned pin) |
203 | { | |
204 | pin -= PIN_BASE; | |
205 | pin /= 32; | |
83f1072e | 206 | return (void *)(at91_pios[pin]); |
177e8a5a SP |
207 | } |
208 | ||
209 | static inline unsigned pin_to_mask(unsigned pin) | |
210 | { | |
211 | pin -= PIN_BASE; | |
212 | return 1 << (pin % 32); | |
213 | } | |
214 | ||
ea8fbba7 JS |
215 | /* The following macros are need for backward compatibility */ |
216 | #define at91_set_GPIO_periph(x, y) \ | |
3ed7c487 | 217 | at91_set_pio_periph((x - PIN_BASE) / 32,(x % 32), y) |
ea8fbba7 JS |
218 | #define at91_set_A_periph(x, y) \ |
219 | at91_set_a_periph((x - PIN_BASE) / 32,(x % 32), y) | |
220 | #define at91_set_B_periph(x, y) \ | |
221 | at91_set_b_periph((x - PIN_BASE) / 32,(x % 32), y) | |
5aaef600 BW |
222 | #define at91_set_gpio_deglitch(x, y) \ |
223 | at91_set_pio_deglitch((x - PIN_BASE) / 32,(x % 32), y) | |
ea8fbba7 JS |
224 | #define at91_set_gpio_output(x, y) \ |
225 | at91_set_pio_output((x - PIN_BASE) / 32,(x % 32), y) | |
226 | #define at91_set_gpio_input(x, y) \ | |
227 | at91_set_pio_input((x - PIN_BASE) / 32,(x % 32), y) | |
177e8a5a | 228 | #endif |
9ecc922e | 229 | |
8c4e4101 WY |
230 | #define at91_set_gpio_value(x, y) \ |
231 | at91_set_pio_value((x / 32), (x % 32), y) | |
232 | #define at91_get_gpio_value(x) \ | |
233 | at91_get_pio_value((x / 32), (x % 32)) | |
234 | ||
9ecc922e AB |
235 | #define GPIO_PIOA_BASE (0) |
236 | #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) | |
237 | #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) | |
238 | #define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) | |
239 | #define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) | |
240 | #define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) | |
241 | #define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) | |
242 | #define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) | |
243 | #define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) | |
244 | #define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) | |
245 | ||
246 | static inline unsigned at91_gpio_to_port(unsigned gpio) | |
247 | { | |
248 | return gpio / 32; | |
249 | } | |
250 | ||
251 | static inline unsigned at91_gpio_to_pin(unsigned gpio) | |
252 | { | |
253 | return gpio % 32; | |
254 | } | |
255 | ||
918354b1 SG |
256 | /* Platform data for each GPIO port */ |
257 | struct at91_port_platdata { | |
258 | uint32_t base_addr; | |
259 | const char *bank_name; | |
260 | }; | |
261 | ||
9ecc922e | 262 | #endif /* __ASM_ARCH_AT91_GPIO_H */ |