]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
bb0fabe4 PF |
2 | /* |
3 | * Copyright 2017 NXP | |
4 | * | |
5 | * Peng Fan <peng.fan@nxp.com> | |
bb0fabe4 PF |
6 | */ |
7 | ||
d678a59d | 8 | #include <common.h> |
09140113 | 9 | #include <command.h> |
bb0fabe4 PF |
10 | #include <asm/arch/clock.h> |
11 | #include <asm/arch/imx-regs.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/arch/sys_proto.h> | |
14 | #include <errno.h> | |
c05ed00a | 15 | #include <linux/delay.h> |
bb0fabe4 PF |
16 | #include <linux/iopoll.h> |
17 | ||
bb0fabe4 PF |
18 | static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; |
19 | ||
712a341c PF |
20 | static u32 get_root_clk(enum clk_root_index clock_id); |
21 | ||
bb0fabe4 PF |
22 | static u32 decode_frac_pll(enum clk_root_src frac_pll) |
23 | { | |
24 | u32 pll_cfg0, pll_cfg1, pllout; | |
25 | u32 pll_refclk_sel, pll_refclk; | |
26 | u32 divr_val, divq_val, divf_val, divff, divfi; | |
27 | u32 pllout_div_shift, pllout_div_mask, pllout_div; | |
28 | ||
29 | switch (frac_pll) { | |
30 | case ARM_PLL_CLK: | |
31 | pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); | |
32 | pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); | |
33 | pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT; | |
34 | pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK; | |
35 | break; | |
36 | default: | |
37 | printf("Frac PLL %d not supporte\n", frac_pll); | |
38 | return 0; | |
39 | } | |
40 | ||
41 | pllout_div = readl(&ana_pll->frac_pllout_div_cfg); | |
42 | pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift; | |
43 | ||
44 | /* Power down */ | |
45 | if (pll_cfg0 & FRAC_PLL_PD_MASK) | |
46 | return 0; | |
47 | ||
48 | /* output not enabled */ | |
49 | if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0) | |
50 | return 0; | |
51 | ||
52 | pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK; | |
53 | ||
54 | if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M) | |
55 | pll_refclk = 25000000u; | |
56 | else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M) | |
57 | pll_refclk = 27000000u; | |
58 | else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M) | |
59 | pll_refclk = 27000000u; | |
60 | else | |
61 | pll_refclk = 0; | |
62 | ||
63 | if (pll_cfg0 & FRAC_PLL_BYPASS_MASK) | |
64 | return pll_refclk; | |
65 | ||
66 | divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >> | |
67 | FRAC_PLL_REFCLK_DIV_VAL_SHIFT; | |
68 | divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK; | |
69 | ||
70 | divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >> | |
71 | FRAC_PLL_FRAC_DIV_CTL_SHIFT; | |
72 | divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; | |
73 | ||
74 | divf_val = 1 + divfi + divff / (1 << 24); | |
75 | ||
76 | pllout = pll_refclk / (divr_val + 1) * 8 * divf_val / | |
77 | ((divq_val + 1) * 2); | |
78 | ||
79 | return pllout / (pllout_div + 1); | |
80 | } | |
81 | ||
82 | static u32 decode_sscg_pll(enum clk_root_src sscg_pll) | |
83 | { | |
84 | u32 pll_cfg0, pll_cfg1, pll_cfg2; | |
85 | u32 pll_refclk_sel, pll_refclk; | |
86 | u32 divr1, divr2, divf1, divf2, divq, div; | |
87 | u32 sse; | |
88 | u32 pll_clke; | |
89 | u32 pllout_div_shift, pllout_div_mask, pllout_div; | |
90 | u32 pllout; | |
91 | ||
92 | switch (sscg_pll) { | |
93 | case SYSTEM_PLL1_800M_CLK: | |
94 | case SYSTEM_PLL1_400M_CLK: | |
95 | case SYSTEM_PLL1_266M_CLK: | |
96 | case SYSTEM_PLL1_200M_CLK: | |
97 | case SYSTEM_PLL1_160M_CLK: | |
98 | case SYSTEM_PLL1_133M_CLK: | |
99 | case SYSTEM_PLL1_100M_CLK: | |
100 | case SYSTEM_PLL1_80M_CLK: | |
101 | case SYSTEM_PLL1_40M_CLK: | |
102 | pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); | |
103 | pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); | |
104 | pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); | |
105 | pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT; | |
106 | pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK; | |
107 | break; | |
108 | case SYSTEM_PLL2_1000M_CLK: | |
109 | case SYSTEM_PLL2_500M_CLK: | |
110 | case SYSTEM_PLL2_333M_CLK: | |
111 | case SYSTEM_PLL2_250M_CLK: | |
112 | case SYSTEM_PLL2_200M_CLK: | |
113 | case SYSTEM_PLL2_166M_CLK: | |
114 | case SYSTEM_PLL2_125M_CLK: | |
115 | case SYSTEM_PLL2_100M_CLK: | |
116 | case SYSTEM_PLL2_50M_CLK: | |
117 | pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); | |
118 | pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); | |
119 | pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); | |
120 | pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT; | |
121 | pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK; | |
122 | break; | |
123 | case SYSTEM_PLL3_CLK: | |
124 | pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0); | |
125 | pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); | |
126 | pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2); | |
127 | pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT; | |
128 | pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK; | |
129 | break; | |
130 | case DRAM_PLL1_CLK: | |
131 | pll_cfg0 = readl(&ana_pll->dram_pll_cfg0); | |
132 | pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); | |
133 | pll_cfg2 = readl(&ana_pll->dram_pll_cfg2); | |
134 | pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT; | |
135 | pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK; | |
136 | break; | |
137 | default: | |
138 | printf("sscg pll %d not supporte\n", sscg_pll); | |
139 | return 0; | |
140 | } | |
141 | ||
142 | switch (sscg_pll) { | |
143 | case DRAM_PLL1_CLK: | |
144 | pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; | |
145 | div = 1; | |
146 | break; | |
147 | case SYSTEM_PLL3_CLK: | |
148 | pll_clke = SSCG_PLL_PLL3_CLKE_MASK; | |
149 | div = 1; | |
150 | break; | |
151 | case SYSTEM_PLL2_1000M_CLK: | |
152 | case SYSTEM_PLL1_800M_CLK: | |
153 | pll_clke = SSCG_PLL_CLKE_MASK; | |
154 | div = 1; | |
155 | break; | |
156 | case SYSTEM_PLL2_500M_CLK: | |
157 | case SYSTEM_PLL1_400M_CLK: | |
158 | pll_clke = SSCG_PLL_DIV2_CLKE_MASK; | |
159 | div = 2; | |
160 | break; | |
161 | case SYSTEM_PLL2_333M_CLK: | |
162 | case SYSTEM_PLL1_266M_CLK: | |
163 | pll_clke = SSCG_PLL_DIV3_CLKE_MASK; | |
164 | div = 3; | |
165 | break; | |
166 | case SYSTEM_PLL2_250M_CLK: | |
167 | case SYSTEM_PLL1_200M_CLK: | |
168 | pll_clke = SSCG_PLL_DIV4_CLKE_MASK; | |
169 | div = 4; | |
170 | break; | |
171 | case SYSTEM_PLL2_200M_CLK: | |
172 | case SYSTEM_PLL1_160M_CLK: | |
173 | pll_clke = SSCG_PLL_DIV5_CLKE_MASK; | |
174 | div = 5; | |
175 | break; | |
176 | case SYSTEM_PLL2_166M_CLK: | |
177 | case SYSTEM_PLL1_133M_CLK: | |
178 | pll_clke = SSCG_PLL_DIV6_CLKE_MASK; | |
179 | div = 6; | |
180 | break; | |
181 | case SYSTEM_PLL2_125M_CLK: | |
182 | case SYSTEM_PLL1_100M_CLK: | |
183 | pll_clke = SSCG_PLL_DIV8_CLKE_MASK; | |
184 | div = 8; | |
185 | break; | |
186 | case SYSTEM_PLL2_100M_CLK: | |
187 | case SYSTEM_PLL1_80M_CLK: | |
188 | pll_clke = SSCG_PLL_DIV10_CLKE_MASK; | |
189 | div = 10; | |
190 | break; | |
191 | case SYSTEM_PLL2_50M_CLK: | |
192 | case SYSTEM_PLL1_40M_CLK: | |
193 | pll_clke = SSCG_PLL_DIV20_CLKE_MASK; | |
194 | div = 20; | |
195 | break; | |
196 | default: | |
197 | printf("sscg pll %d not supporte\n", sscg_pll); | |
198 | return 0; | |
199 | } | |
200 | ||
201 | /* Power down */ | |
202 | if (pll_cfg0 & SSCG_PLL_PD_MASK) | |
203 | return 0; | |
204 | ||
205 | /* output not enabled */ | |
206 | if ((pll_cfg0 & pll_clke) == 0) | |
207 | return 0; | |
208 | ||
209 | pllout_div = readl(&ana_pll->sscg_pllout_div_cfg); | |
210 | pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift; | |
211 | ||
212 | pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK; | |
213 | ||
214 | if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M) | |
215 | pll_refclk = 25000000u; | |
216 | else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M) | |
217 | pll_refclk = 27000000u; | |
218 | else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M) | |
219 | pll_refclk = 27000000u; | |
220 | else | |
221 | pll_refclk = 0; | |
222 | ||
223 | /* We assume bypass1/2 are the same value */ | |
224 | if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) || | |
225 | (pll_cfg0 & SSCG_PLL_BYPASS2_MASK)) | |
226 | return pll_refclk; | |
227 | ||
228 | divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> | |
229 | SSCG_PLL_REF_DIVR1_SHIFT; | |
230 | divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> | |
231 | SSCG_PLL_REF_DIVR2_SHIFT; | |
232 | divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >> | |
233 | SSCG_PLL_FEEDBACK_DIV_F1_SHIFT; | |
234 | divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >> | |
235 | SSCG_PLL_FEEDBACK_DIV_F2_SHIFT; | |
236 | divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> | |
237 | SSCG_PLL_OUTPUT_DIV_VAL_SHIFT; | |
238 | sse = pll_cfg1 & SSCG_PLL_SSE_MASK; | |
239 | ||
240 | if (sse) | |
241 | sse = 8; | |
242 | else | |
243 | sse = 2; | |
244 | ||
245 | pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / | |
246 | (divr2 + 1) * (divf2 + 1) / (divq + 1); | |
247 | ||
248 | return pllout / (pllout_div + 1) / div; | |
249 | } | |
250 | ||
251 | static u32 get_root_src_clk(enum clk_root_src root_src) | |
252 | { | |
253 | switch (root_src) { | |
254 | case OSC_25M_CLK: | |
255 | return 25000000; | |
256 | case OSC_27M_CLK: | |
d4a0c098 | 257 | return 27000000; |
bb0fabe4 | 258 | case OSC_32K_CLK: |
d4a0c098 | 259 | return 32768; |
bb0fabe4 PF |
260 | case ARM_PLL_CLK: |
261 | return decode_frac_pll(root_src); | |
262 | case SYSTEM_PLL1_800M_CLK: | |
263 | case SYSTEM_PLL1_400M_CLK: | |
264 | case SYSTEM_PLL1_266M_CLK: | |
265 | case SYSTEM_PLL1_200M_CLK: | |
266 | case SYSTEM_PLL1_160M_CLK: | |
267 | case SYSTEM_PLL1_133M_CLK: | |
268 | case SYSTEM_PLL1_100M_CLK: | |
269 | case SYSTEM_PLL1_80M_CLK: | |
270 | case SYSTEM_PLL1_40M_CLK: | |
271 | case SYSTEM_PLL2_1000M_CLK: | |
272 | case SYSTEM_PLL2_500M_CLK: | |
273 | case SYSTEM_PLL2_333M_CLK: | |
274 | case SYSTEM_PLL2_250M_CLK: | |
275 | case SYSTEM_PLL2_200M_CLK: | |
276 | case SYSTEM_PLL2_166M_CLK: | |
277 | case SYSTEM_PLL2_125M_CLK: | |
278 | case SYSTEM_PLL2_100M_CLK: | |
279 | case SYSTEM_PLL2_50M_CLK: | |
280 | case SYSTEM_PLL3_CLK: | |
281 | return decode_sscg_pll(root_src); | |
712a341c PF |
282 | case ARM_A53_ALT_CLK: |
283 | return get_root_clk(ARM_A53_CLK_ROOT); | |
bb0fabe4 PF |
284 | default: |
285 | return 0; | |
286 | } | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static u32 get_root_clk(enum clk_root_index clock_id) | |
292 | { | |
293 | enum clk_root_src root_src; | |
294 | u32 post_podf, pre_podf, root_src_clk; | |
295 | ||
296 | if (clock_root_enabled(clock_id) <= 0) | |
297 | return 0; | |
298 | ||
299 | if (clock_get_prediv(clock_id, &pre_podf) < 0) | |
300 | return 0; | |
301 | ||
302 | if (clock_get_postdiv(clock_id, &post_podf) < 0) | |
303 | return 0; | |
304 | ||
305 | if (clock_get_src(clock_id, &root_src) < 0) | |
306 | return 0; | |
307 | ||
308 | root_src_clk = get_root_src_clk(root_src); | |
309 | ||
310 | return root_src_clk / (post_podf + 1) / (pre_podf + 1); | |
311 | } | |
312 | ||
41b230bf YL |
313 | #ifdef CONFIG_IMX_HAB |
314 | void hab_caam_clock_enable(unsigned char enable) | |
315 | { | |
316 | /* The CAAM clock is always on for iMX8M */ | |
317 | } | |
318 | #endif | |
319 | ||
bb0fabe4 PF |
320 | #ifdef CONFIG_MXC_OCOTP |
321 | void enable_ocotp_clk(unsigned char enable) | |
322 | { | |
323 | clock_enable(CCGR_OCOTP, !!enable); | |
324 | } | |
325 | #endif | |
326 | ||
327 | int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) | |
328 | { | |
329 | /* 0 - 3 is valid i2c num */ | |
330 | if (i2c_num > 3) | |
331 | return -EINVAL; | |
332 | ||
333 | clock_enable(CCGR_I2C1 + i2c_num, !!enable); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
712a341c PF |
338 | u32 get_arm_core_clk(void) |
339 | { | |
340 | enum clk_root_src root_src; | |
341 | u32 root_src_clk; | |
342 | ||
343 | if (clock_get_src(CORE_SEL_CFG, &root_src) < 0) | |
344 | return 0; | |
345 | ||
346 | root_src_clk = get_root_src_clk(root_src); | |
347 | ||
348 | return root_src_clk; | |
349 | } | |
350 | ||
8838cdf1 | 351 | unsigned int mxc_get_clock(enum mxc_clock clk) |
bb0fabe4 PF |
352 | { |
353 | u32 val; | |
354 | ||
712a341c | 355 | switch (clk) { |
392a4e6d | 356 | case MXC_ARM_CLK: |
712a341c | 357 | return get_arm_core_clk(); |
392a4e6d | 358 | case MXC_IPG_CLK: |
bb0fabe4 PF |
359 | clock_get_target_val(IPG_CLK_ROOT, &val); |
360 | val = val & 0x3; | |
361 | return get_root_clk(AHB_CLK_ROOT) / (val + 1); | |
6ff55bcd HT |
362 | case MXC_CSPI_CLK: |
363 | return get_root_clk(ECSPI1_CLK_ROOT); | |
392a4e6d PF |
364 | case MXC_ESDHC_CLK: |
365 | return get_root_clk(USDHC1_CLK_ROOT); | |
366 | case MXC_ESDHC2_CLK: | |
367 | return get_root_clk(USDHC2_CLK_ROOT); | |
6ff55bcd HT |
368 | case MXC_I2C_CLK: |
369 | return get_root_clk(I2C1_CLK_ROOT); | |
370 | case MXC_UART_CLK: | |
371 | return get_root_clk(UART1_CLK_ROOT); | |
372 | case MXC_QSPI_CLK: | |
373 | return get_root_clk(QSPI_CLK_ROOT); | |
392a4e6d PF |
374 | default: |
375 | return get_root_clk(clk); | |
bb0fabe4 | 376 | } |
bb0fabe4 PF |
377 | } |
378 | ||
379 | u32 imx_get_uartclk(void) | |
380 | { | |
381 | return mxc_get_clock(UART1_CLK_ROOT); | |
382 | } | |
383 | ||
384 | void mxs_set_lcdclk(u32 base_addr, u32 freq) | |
385 | { | |
386 | /* | |
387 | * LCDIF_PIXEL_CLK: select 800MHz root clock, | |
388 | * select pre divider 8, output is 100 MHz | |
389 | */ | |
390 | clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | | |
391 | CLK_ROOT_SOURCE_SEL(4) | | |
392 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8)); | |
393 | } | |
394 | ||
395 | void init_wdog_clk(void) | |
396 | { | |
397 | clock_enable(CCGR_WDOG1, 0); | |
398 | clock_enable(CCGR_WDOG2, 0); | |
399 | clock_enable(CCGR_WDOG3, 0); | |
400 | clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | | |
401 | CLK_ROOT_SOURCE_SEL(0)); | |
402 | clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | | |
403 | CLK_ROOT_SOURCE_SEL(0)); | |
404 | clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | | |
405 | CLK_ROOT_SOURCE_SEL(0)); | |
406 | clock_enable(CCGR_WDOG1, 1); | |
407 | clock_enable(CCGR_WDOG2, 1); | |
408 | clock_enable(CCGR_WDOG3, 1); | |
409 | } | |
410 | ||
4a837d43 YL |
411 | void init_usb_clk(void) |
412 | { | |
413 | if (!is_usb_boot()) { | |
414 | clock_enable(CCGR_USB_CTRL1, 0); | |
415 | clock_enable(CCGR_USB_CTRL2, 0); | |
416 | clock_enable(CCGR_USB_PHY1, 0); | |
417 | clock_enable(CCGR_USB_PHY2, 0); | |
418 | /* 500MHz */ | |
419 | clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | | |
420 | CLK_ROOT_SOURCE_SEL(1)); | |
421 | /* 100MHz */ | |
422 | clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | | |
423 | CLK_ROOT_SOURCE_SEL(1)); | |
424 | /* 100MHz */ | |
425 | clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | | |
426 | CLK_ROOT_SOURCE_SEL(1)); | |
427 | clock_enable(CCGR_USB_CTRL1, 1); | |
428 | clock_enable(CCGR_USB_CTRL2, 1); | |
429 | clock_enable(CCGR_USB_PHY1, 1); | |
430 | clock_enable(CCGR_USB_PHY2, 1); | |
431 | } | |
432 | } | |
bb0fabe4 | 433 | |
2dfecdd1 PF |
434 | void init_nand_clk(void) |
435 | { | |
436 | clock_enable(CCGR_RAWNAND, 0); | |
437 | clock_set_target_val(NAND_CLK_ROOT, | |
438 | CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) | | |
439 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); | |
440 | clock_enable(CCGR_RAWNAND, 1); | |
441 | } | |
442 | ||
bb0fabe4 PF |
443 | void init_uart_clk(u32 index) |
444 | { | |
445 | /* Set uart clock root 25M OSC */ | |
446 | switch (index) { | |
447 | case 0: | |
448 | clock_enable(CCGR_UART1, 0); | |
449 | clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | | |
450 | CLK_ROOT_SOURCE_SEL(0)); | |
451 | clock_enable(CCGR_UART1, 1); | |
452 | return; | |
453 | case 1: | |
454 | clock_enable(CCGR_UART2, 0); | |
455 | clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | | |
456 | CLK_ROOT_SOURCE_SEL(0)); | |
457 | clock_enable(CCGR_UART2, 1); | |
458 | return; | |
459 | case 2: | |
460 | clock_enable(CCGR_UART3, 0); | |
461 | clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | | |
462 | CLK_ROOT_SOURCE_SEL(0)); | |
463 | clock_enable(CCGR_UART3, 1); | |
464 | return; | |
465 | case 3: | |
466 | clock_enable(CCGR_UART4, 0); | |
467 | clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | | |
468 | CLK_ROOT_SOURCE_SEL(0)); | |
469 | clock_enable(CCGR_UART4, 1); | |
470 | return; | |
471 | default: | |
472 | printf("Invalid uart index\n"); | |
473 | return; | |
474 | } | |
475 | } | |
476 | ||
477 | void init_clk_usdhc(u32 index) | |
478 | { | |
479 | /* | |
480 | * set usdhc clock root | |
481 | * sys pll1 400M | |
482 | */ | |
483 | switch (index) { | |
484 | case 0: | |
485 | clock_enable(CCGR_USDHC1, 0); | |
486 | clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | | |
15a74260 | 487 | CLK_ROOT_SOURCE_SEL(1)); |
bb0fabe4 PF |
488 | clock_enable(CCGR_USDHC1, 1); |
489 | return; | |
490 | case 1: | |
491 | clock_enable(CCGR_USDHC2, 0); | |
492 | clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | | |
15a74260 | 493 | CLK_ROOT_SOURCE_SEL(1)); |
bb0fabe4 PF |
494 | clock_enable(CCGR_USDHC2, 1); |
495 | return; | |
496 | default: | |
497 | printf("Invalid usdhc index\n"); | |
498 | return; | |
499 | } | |
500 | } | |
501 | ||
502 | int set_clk_qspi(void) | |
503 | { | |
504 | /* | |
505 | * set qspi root | |
506 | * sys pll1 100M | |
507 | */ | |
508 | clock_enable(CCGR_QSPI, 0); | |
509 | clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | | |
510 | CLK_ROOT_SOURCE_SEL(7)); | |
511 | clock_enable(CCGR_QSPI, 1); | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | #ifdef CONFIG_FEC_MXC | |
517 | int set_clk_enet(enum enet_freq type) | |
518 | { | |
519 | u32 target; | |
520 | u32 enet1_ref; | |
521 | ||
522 | switch (type) { | |
523 | case ENET_125MHZ: | |
524 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; | |
525 | break; | |
526 | case ENET_50MHZ: | |
527 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; | |
528 | break; | |
529 | case ENET_25MHZ: | |
530 | enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; | |
531 | break; | |
532 | default: | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | /* disable the clock first */ | |
537 | clock_enable(CCGR_ENET1, 0); | |
538 | clock_enable(CCGR_SIM_ENET, 0); | |
539 | ||
540 | /* set enet axi clock 266Mhz */ | |
541 | target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | | |
542 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | | |
543 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); | |
544 | clock_set_target_val(ENET_AXI_CLK_ROOT, target); | |
545 | ||
546 | target = CLK_ROOT_ON | enet1_ref | | |
547 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | | |
548 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); | |
549 | clock_set_target_val(ENET_REF_CLK_ROOT, target); | |
550 | ||
551 | target = CLK_ROOT_ON | | |
552 | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | | |
553 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | | |
554 | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); | |
555 | clock_set_target_val(ENET_TIMER_CLK_ROOT, target); | |
556 | ||
557 | /* enable clock */ | |
558 | clock_enable(CCGR_SIM_ENET, 1); | |
559 | clock_enable(CCGR_ENET1, 1); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | #endif | |
564 | ||
565 | u32 imx_get_fecclk(void) | |
566 | { | |
567 | return get_root_clk(ENET_AXI_CLK_ROOT); | |
568 | } | |
569 | ||
b3e5cb8d PF |
570 | static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { |
571 | DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, | |
572 | CLK_ROOT_PRE_DIV2), | |
573 | DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, | |
574 | CLK_ROOT_PRE_DIV2), | |
575 | DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, | |
576 | CLK_ROOT_PRE_DIV2), | |
577 | }; | |
578 | ||
579 | void dram_enable_bypass(ulong clk_val) | |
bb0fabe4 | 580 | { |
b3e5cb8d PF |
581 | int i; |
582 | struct dram_bypass_clk_setting *config; | |
bb0fabe4 | 583 | |
b3e5cb8d PF |
584 | for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) { |
585 | if (clk_val == imx8mq_dram_bypass_tbl[i].clk) | |
586 | break; | |
587 | } | |
bb0fabe4 | 588 | |
b3e5cb8d PF |
589 | if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) { |
590 | printf("No matched freq table %lu\n", clk_val); | |
591 | return; | |
592 | } | |
593 | ||
594 | config = &imx8mq_dram_bypass_tbl[i]; | |
595 | ||
596 | clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | | |
597 | CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | | |
598 | CLK_ROOT_PRE_DIV(config->alt_pre_div)); | |
599 | clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | | |
600 | CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | | |
601 | CLK_ROOT_PRE_DIV(config->apb_pre_div)); | |
602 | clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | | |
603 | CLK_ROOT_SOURCE_SEL(1)); | |
604 | } | |
605 | ||
606 | void dram_disable_bypass(void) | |
607 | { | |
608 | clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | | |
609 | CLK_ROOT_SOURCE_SEL(0)); | |
610 | clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | | |
611 | CLK_ROOT_SOURCE_SEL(4) | | |
612 | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); | |
613 | } | |
bb0fabe4 | 614 | |
b3e5cb8d PF |
615 | #ifdef CONFIG_SPL_BUILD |
616 | void dram_pll_init(ulong pll_val) | |
617 | { | |
618 | u32 val; | |
619 | void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; | |
620 | void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; | |
621 | ||
622 | /* Bypass */ | |
623 | setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); | |
624 | setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); | |
625 | ||
626 | switch (pll_val) { | |
627 | case MHZ(800): | |
628 | val = readl(pll_cfg_reg2); | |
629 | val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | | |
630 | SSCG_PLL_FEEDBACK_DIV_F2_MASK | | |
631 | SSCG_PLL_FEEDBACK_DIV_F1_MASK | | |
632 | SSCG_PLL_REF_DIVR2_MASK); | |
633 | val |= SSCG_PLL_OUTPUT_DIV_VAL(0); | |
634 | val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); | |
635 | val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); | |
636 | val |= SSCG_PLL_REF_DIVR2_VAL(29); | |
637 | writel(val, pll_cfg_reg2); | |
638 | break; | |
639 | case MHZ(600): | |
640 | val = readl(pll_cfg_reg2); | |
641 | val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | | |
642 | SSCG_PLL_FEEDBACK_DIV_F2_MASK | | |
643 | SSCG_PLL_FEEDBACK_DIV_F1_MASK | | |
644 | SSCG_PLL_REF_DIVR2_MASK); | |
645 | val |= SSCG_PLL_OUTPUT_DIV_VAL(1); | |
646 | val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17); | |
647 | val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); | |
648 | val |= SSCG_PLL_REF_DIVR2_VAL(29); | |
649 | writel(val, pll_cfg_reg2); | |
650 | break; | |
651 | case MHZ(400): | |
652 | val = readl(pll_cfg_reg2); | |
653 | val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | | |
654 | SSCG_PLL_FEEDBACK_DIV_F2_MASK | | |
655 | SSCG_PLL_FEEDBACK_DIV_F1_MASK | | |
656 | SSCG_PLL_REF_DIVR2_MASK); | |
657 | val |= SSCG_PLL_OUTPUT_DIV_VAL(1); | |
658 | val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); | |
659 | val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); | |
660 | val |= SSCG_PLL_REF_DIVR2_VAL(29); | |
661 | writel(val, pll_cfg_reg2); | |
662 | break; | |
663 | case MHZ(167): | |
664 | val = readl(pll_cfg_reg2); | |
665 | val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | | |
666 | SSCG_PLL_FEEDBACK_DIV_F2_MASK | | |
667 | SSCG_PLL_FEEDBACK_DIV_F1_MASK | | |
668 | SSCG_PLL_REF_DIVR2_MASK); | |
669 | val |= SSCG_PLL_OUTPUT_DIV_VAL(3); | |
670 | val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8); | |
671 | val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45); | |
672 | val |= SSCG_PLL_REF_DIVR2_VAL(30); | |
673 | writel(val, pll_cfg_reg2); | |
674 | break; | |
675 | default: | |
676 | break; | |
677 | } | |
bb0fabe4 PF |
678 | |
679 | /* Clear power down bit */ | |
b3e5cb8d | 680 | clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK); |
bb0fabe4 | 681 | /* Eanble ARM_PLL/SYS_PLL */ |
b3e5cb8d | 682 | setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK); |
bb0fabe4 PF |
683 | |
684 | /* Clear bypass */ | |
b3e5cb8d | 685 | clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); |
bb0fabe4 | 686 | __udelay(100); |
b3e5cb8d | 687 | clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); |
bb0fabe4 | 688 | /* Wait lock */ |
b3e5cb8d PF |
689 | while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK)) |
690 | ; | |
bb0fabe4 PF |
691 | } |
692 | ||
2f39ab16 | 693 | static int frac_pll_init(u32 pll, enum frac_pll_out_val val) |
bb0fabe4 PF |
694 | { |
695 | void __iomem *pll_cfg0, __iomem *pll_cfg1; | |
712a341c | 696 | u32 val_cfg0, val_cfg1, divq; |
bb0fabe4 PF |
697 | int ret; |
698 | ||
699 | switch (pll) { | |
700 | case ANATOP_ARM_PLL: | |
701 | pll_cfg0 = &ana_pll->arm_pll_cfg0; | |
702 | pll_cfg1 = &ana_pll->arm_pll_cfg1; | |
703 | ||
712a341c | 704 | if (val == FRAC_PLL_OUT_1000M) { |
bb0fabe4 | 705 | val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49); |
712a341c PF |
706 | divq = 0; |
707 | } else { | |
bb0fabe4 | 708 | val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79); |
712a341c PF |
709 | divq = 1; |
710 | } | |
bb0fabe4 PF |
711 | val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | |
712 | FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK | | |
713 | FRAC_PLL_REFCLK_DIV_VAL(4) | | |
712a341c | 714 | FRAC_PLL_OUTPUT_DIV_VAL(divq); |
bb0fabe4 PF |
715 | break; |
716 | default: | |
717 | return -EINVAL; | |
718 | } | |
719 | ||
720 | /* bypass the clock */ | |
721 | setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); | |
722 | /* Set the value */ | |
723 | writel(val_cfg1, pll_cfg1); | |
724 | writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); | |
725 | val_cfg0 = readl(pll_cfg0); | |
726 | /* unbypass the clock */ | |
727 | clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); | |
728 | ret = readl_poll_timeout(pll_cfg0, val_cfg0, | |
729 | val_cfg0 & FRAC_PLL_LOCK_MASK, 1); | |
730 | if (ret) | |
731 | printf("%s timeout\n", __func__); | |
732 | clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK); | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
bb0fabe4 PF |
737 | |
738 | int clock_init(void) | |
739 | { | |
740 | u32 grade; | |
741 | ||
742 | clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | | |
743 | CLK_ROOT_SOURCE_SEL(0)); | |
744 | ||
745 | /* | |
746 | * 8MQ only supports two grades: consumer and industrial. | |
747 | * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial | |
748 | */ | |
749 | grade = get_cpu_temp_grade(NULL, NULL); | |
712a341c | 750 | if (!grade) |
bb0fabe4 | 751 | frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M); |
712a341c PF |
752 | else |
753 | frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M); | |
754 | ||
755 | /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */ | |
756 | clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1)); | |
757 | ||
bb0fabe4 PF |
758 | /* |
759 | * According to ANAMIX SPEC | |
760 | * sys pll1 fixed at 800MHz | |
761 | * sys pll2 fixed at 1GHz | |
762 | * Here we only enable the outputs. | |
763 | */ | |
764 | setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK | | |
765 | SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK | | |
766 | SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK | | |
767 | SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK | | |
768 | SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK); | |
769 | ||
770 | setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK | | |
771 | SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK | | |
772 | SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK | | |
773 | SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK | | |
774 | SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK); | |
775 | ||
776 | clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | | |
777 | CLK_ROOT_SOURCE_SEL(1)); | |
778 | ||
779 | init_wdog_clk(); | |
780 | clock_enable(CCGR_TSENSOR, 1); | |
9e094455 | 781 | clock_enable(CCGR_OCOTP, 1); |
bb0fabe4 | 782 | |
eeca15a5 PF |
783 | /* config GIC ROOT to sys_pll2_200m */ |
784 | clock_enable(CCGR_GIC, 0); | |
785 | clock_set_target_val(GIC_CLK_ROOT, | |
786 | CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); | |
787 | clock_enable(CCGR_GIC, 1); | |
788 | ||
bb0fabe4 PF |
789 | return 0; |
790 | } | |
791 | #endif | |
792 | ||
793 | /* | |
794 | * Dump some clockes. | |
795 | */ | |
796 | #ifndef CONFIG_SPL_BUILD | |
09140113 SG |
797 | static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, |
798 | char *const argv[]) | |
bb0fabe4 PF |
799 | { |
800 | u32 freq; | |
801 | ||
802 | freq = decode_frac_pll(ARM_PLL_CLK); | |
803 | printf("ARM_PLL %8d MHz\n", freq / 1000000); | |
6fcd0b23 YL |
804 | freq = decode_sscg_pll(DRAM_PLL1_CLK); |
805 | printf("DRAM_PLL %8d MHz\n", freq / 1000000); | |
bb0fabe4 PF |
806 | freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK); |
807 | printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000); | |
808 | freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK); | |
809 | printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000); | |
810 | freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK); | |
811 | printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000); | |
812 | freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK); | |
813 | printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000); | |
814 | freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK); | |
815 | printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000); | |
816 | freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK); | |
817 | printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000); | |
818 | freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK); | |
819 | printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000); | |
820 | freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK); | |
821 | printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000); | |
822 | freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK); | |
823 | printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000); | |
824 | freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK); | |
825 | printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000); | |
826 | freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK); | |
827 | printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000); | |
828 | freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK); | |
829 | printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000); | |
830 | freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK); | |
831 | printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000); | |
832 | freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK); | |
833 | printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000); | |
834 | freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK); | |
835 | printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000); | |
836 | freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK); | |
837 | printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000); | |
838 | freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK); | |
839 | printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000); | |
840 | freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK); | |
841 | printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000); | |
842 | freq = decode_sscg_pll(SYSTEM_PLL3_CLK); | |
843 | printf("SYS_PLL3 %8d MHz\n", freq / 1000000); | |
844 | freq = mxc_get_clock(UART1_CLK_ROOT); | |
845 | printf("UART1 %8d MHz\n", freq / 1000000); | |
846 | freq = mxc_get_clock(USDHC1_CLK_ROOT); | |
847 | printf("USDHC1 %8d MHz\n", freq / 1000000); | |
848 | freq = mxc_get_clock(QSPI_CLK_ROOT); | |
849 | printf("QSPI %8d MHz\n", freq / 1000000); | |
850 | return 0; | |
851 | } | |
852 | ||
853 | U_BOOT_CMD( | |
cd357ad1 | 854 | clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks, |
bb0fabe4 PF |
855 | "display clocks", |
856 | "" | |
857 | ); | |
858 | #endif |