[thirdparty/u-boot.git] / arch / arm / mach-imx / imx8ulp / rdc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2021 NXP
 */

#include <common.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/mu_hal.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/arch/rdc.h>
#include <div64.h>

#define XRDC_ADDR	0x292f0000
#define MRC_OFFSET	0x2000
#define MRC_STEP	0x200

#define SP(X)		((X) << 9)
#define SU(X)		((X) << 6)
#define NP(X)		((X) << 3)
#define NU(X)		((X) << 0)

#define RWX		7
#define RW		6
#define R		4
#define X		1

#define D7SEL_CODE	(SP(RW) | SU(RW) | NP(RWX) | NU(RWX))
#define D6SEL_CODE	(SP(RW) | SU(RW) | NP(RWX))
#define D5SEL_CODE	(SP(RW) | SU(RWX))
#define D4SEL_CODE	SP(RWX)
#define D3SEL_CODE	(SP(X) | SU(X) | NP(X) | NU(X))
#define D0SEL_CODE	0

#define D7SEL_DAT	(SP(RW) | SU(RW) | NP(RW) | NU(RW))
#define D6SEL_DAT	(SP(RW) | SU(RW) | NP(RW))
#define D5SEL_DAT	(SP(RW) | SU(RW) | NP(R) | NU(R))
#define D4SEL_DAT	(SP(RW) | SU(RW))
#define D3SEL_DAT	SP(RW)

struct mbc_mem_dom {
	u32 mem_glbcfg[4];
	u32 nse_blk_index;
	u32 nse_blk_set;
	u32 nse_blk_clr;
	u32 nsr_blk_clr_all;
	u32 memn_glbac[8];
	/* The upper only existed in the beginning of each MBC */
	u32 mem0_blk_cfg_w[64];
	u32 mem0_blk_nse_w[16];
	u32 mem1_blk_cfg_w[8];
	u32 mem1_blk_nse_w[2];
	u32 mem2_blk_cfg_w[8];
	u32 mem2_blk_nse_w[2];
	u32 mem3_blk_cfg_w[8];
	u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
	u32 reserved[2];
};

struct mrc_rgn_dom {
	u32 mrc_glbcfg[4];
	u32 nse_rgn_indirect;
	u32 nse_rgn_set;
	u32 nse_rgn_clr;
	u32 nse_rgn_clr_all;
	u32 memn_glbac[8];
	/* The upper only existed in the beginning of each MRC */
	u32 rgn_desc_words[8][2]; /* 8 regions, 2 words per region */
	u32 reserved[16];
	u32	rgn_nse;
	u32 reserved2[15];
};

struct trdc {
	u8 res0[0x1000];
	struct mbc_mem_dom mem_dom[4][8];
	struct mrc_rgn_dom mrc_dom[2][8];
};

union dxsel_perm {
	struct {
		u8 dx;
		u8 perm;
	};

	u32 dom_perm;
};

int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel)
{
	ulong w2_addr;
	u32 val = 0;

	w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8;

	val = (readl(w2_addr) & (~(7 << (3 * dom)))) | (dxsel << (3 * dom));
	writel(val, w2_addr);

	return 0;
}

int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size)
{
	ulong w0_addr, w1_addr;

	w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
	w1_addr = w0_addr + 4;

	if ((size % 32) != 0)
		return -EINVAL;

	writel(w0 & ~0x1f, w0_addr);
	writel(w0 + size - 1, w1_addr);

	return 0;
}

int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4)
{
	ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC;
	ulong w4_addr = w3_addr + 4;

	writel(w3, w3_addr);
	writel(w4, w4_addr);

	return 0;
}

int xrdc_config_pdac_openacc(u32 bridge, u32 index)
{
	ulong w0_addr;
	u32 val;

	switch (bridge) {
	case 3:
		w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
		break;
	case 4:
		w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
		break;
	case 5:
		w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
		break;
	default:
		return -EINVAL;
	}
	writel(0xffffff, w0_addr);

	val = readl(w0_addr + 4);
	writel(val | BIT(31), w0_addr + 4);

	return 0;
}

int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
{
	ulong w0_addr;
	u32 val;

	switch (bridge) {
	case 3:
		w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
		break;
	case 4:
		w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
		break;
	case 5:
		w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
		break;
	default:
		return -EINVAL;
	}
	val = readl(w0_addr);
	writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);

	val = readl(w0_addr + 4);
	writel(val | BIT(31), w0_addr + 4);

	return 0;
}

int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
{
	ulong w0_addr;
	u32 val;

	if (msc > 2)
		return -EINVAL;

	w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;

	val = readl(w0_addr);
	writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);

	val = readl(w0_addr + 4);
	writel(val | BIT(31), w0_addr + 4);

	return 0;
}

int release_rdc(enum rdc_type type)
{
	ulong s_mu_base = 0x27020000UL;
	struct ele_msg msg;
	int ret;
	u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;

	msg.version = ELE_VERSION;
	msg.tag = ELE_CMD_TAG;
	msg.size = 2;
	msg.command = ELE_RELEASE_RDC_REQ;
	msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */

	mu_hal_init(s_mu_base);
	mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
	mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);

	ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
	if (!ret) {
		ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
		if (!ret) {
			if ((msg.data[0] & 0xff) == 0xd6)
				return 0;
		}

		return -EIO;
	}

	return ret;
}

void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
{
	ulong xrdc_base = 0x292f0000, off;
	u32 mrgd[5];
	u8 mrcfg, j, region_num;
	u8 dsel;

	mrcfg = readb(xrdc_base + 0x140 + mrc_index);
	region_num = mrcfg & 0x1f;

	for (j = 0; j < region_num; j++) {
		off = 0x2000 + mrc_index * 0x200 + j * 0x20;

		mrgd[0] = readl(xrdc_base + off);
		mrgd[1] = readl(xrdc_base + off + 4);
		mrgd[2] = readl(xrdc_base + off + 8);
		mrgd[3] = readl(xrdc_base + off + 0xc);
		mrgd[4] = readl(xrdc_base + off + 0x10);

		debug("MRC [%u][%u]\n", mrc_index, j);
		debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
		      mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]);

		/* hit */
		if (addr >= mrgd[0] && addr <= mrgd[1]) {
			/* find domain 7 DSEL */
			dsel = (mrgd[2] >> 21) & 0x7;
			if (dsel == 1) {
				mrgd[4] &= ~0xFFF;
				mrgd[4] |= (access & 0xFFF);
			} else if (dsel == 2) {
				mrgd[4] &= ~0xFFF0000;
				mrgd[4] |= ((access & 0xFFF) << 16);
			}

			/* not handle other cases, since ELE only set ACCESS1 and 2 */
			writel(mrgd[4], xrdc_base + off + 0x10);
			return;
		}
	}
}

void xrdc_init_mda(void)
{
	ulong xrdc_base = XRDC_ADDR, off;
	u32 i = 0;

	/* Set MDA3-5 for PXP, ENET, CAAM to DID 1*/
	for (i = 3; i <= 5; i++) {
		off = 0x800 + i * 0x20;
		writel(0x200000A1, xrdc_base + off);
		writel(0xA00000A1, xrdc_base + off);
	}

	/* Set MDA10 -15 to DID 3 for video */
	for (i = 10; i <= 15; i++) {
		off = 0x800 + i * 0x20;
		writel(0x200000A3, xrdc_base + off);
		writel(0xA00000A3, xrdc_base + off);
	}
}

void xrdc_init_mrc(void)
{
	/* Re-config MRC3 for SRAM0 in case protected by ELE */
	xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
	xrdc_config_mrc_dx_perm(3, 0, 0, 1);
	xrdc_config_mrc_dx_perm(3, 0, 1, 1);
	xrdc_config_mrc_dx_perm(3, 0, 4, 1);
	xrdc_config_mrc_dx_perm(3, 0, 5, 1);
	xrdc_config_mrc_dx_perm(3, 0, 6, 1);
	xrdc_config_mrc_dx_perm(3, 0, 7, 1);
	xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF);

	/* Clear other 3 regions of MRC3 to invalid */
	xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0);
	xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0);
	xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0);

	/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
	xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
	xrdc_config_mrc_dx_perm(4, 0, 1, 1);
	xrdc_config_mrc_dx_perm(4, 0, 7, 1);
	xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);

	xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
	xrdc_config_mrc_dx_perm(5, 0, 1, 1);
	xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);

	/* Set MRC6 for DDR access from ELE */
	xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
	xrdc_config_mrc_dx_perm(6, 0, 4, 1);
	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);

	/* The MRC8 is for SRAM1 */
	xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
	/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
	xrdc_config_mrc_dx_perm(8, 0, 0, 1);
	xrdc_config_mrc_dx_perm(8, 0, 1, 1);
	xrdc_config_mrc_dx_perm(8, 0, 2, 1);
	xrdc_config_mrc_dx_perm(8, 0, 3, 1);
	xrdc_config_mrc_dx_perm(8, 0, 4, 1);
	xrdc_config_mrc_dx_perm(8, 0, 5, 1);
	xrdc_config_mrc_dx_perm(8, 0, 6, 1);
	xrdc_config_mrc_dx_perm(8, 0, 7, 1);
	xrdc_config_mrc_w3_w4(8, 0, 0x0, 0x80000FFF);

	/* The MRC6 is for video modules to ddr */
	xrdc_config_mrc_w0_w1(6, 0, 0x80000000, 0x80000000);
	xrdc_config_mrc_dx_perm(6, 0, 3, 1); /* allow for domain 3 video */
	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
}

void xrdc_init_pdac_msc(void)
{
	/* Init LPAV PDAC and MSC for DDR init */
	xrdc_config_pdac(5, 36, 6, 0x7); /* CMC2*/
	xrdc_config_pdac(5, 36, 7, 0x7);
	xrdc_config_pdac(5, 37, 6, 0x7); /* SIM2 */
	xrdc_config_pdac(5, 37, 7, 0x7);
	xrdc_config_pdac(5, 38, 6, 0x7); /* CGC2 */
	xrdc_config_pdac(5, 38, 7, 0x7);
	xrdc_config_pdac(5, 39, 6, 0x7); /* PCC5 */
	xrdc_config_pdac(5, 39, 7, 0x7);

	xrdc_config_msc(0, 0, 6, 0x7); /* GPIOE */
	xrdc_config_msc(0, 0, 7, 0x7);
	xrdc_config_msc(0, 1, 6, 0x7); /* GPIOF */
	xrdc_config_msc(0, 1, 7, 0x7);
	xrdc_config_msc(1, 0, 6, 0x7); /* GPIOD */
	xrdc_config_msc(1, 0, 7, 0x7);
	xrdc_config_msc(2, 6, 6, 0x7); /* DDR controller */
	xrdc_config_msc(2, 6, 7, 0x7);
}

int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access)
{
	struct trdc *trdc_base = (struct trdc *)0x28031000U;
	struct mbc_mem_dom *mbc_dom;
	u32 *cfg_w, *nse_w;
	u32 index, offset, val;

	mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x];

	switch (mem_x) {
	case 0:
		cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
		nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
		break;
	case 1:
		cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
		nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
		break;
	case 2:
		cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
		nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
		break;
	case 3:
		cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
		nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
		break;
	default:
		return -EINVAL;
	};

	index = blk_x % 8;
	offset = index * 4;

	val = readl((void __iomem *)cfg_w);

	val &= ~(0xFU << offset);

	/* MBC0-3
	 *  Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
	 *  So select MBC0_MEMN_GLBAC0
	 */
	if (sec_access) {
		val |= (0x0 << offset);
		writel(val, (void __iomem *)cfg_w);
	} else {
		val |= (0x8 << offset); /* nse bit set */
		writel(val, (void __iomem *)cfg_w);
	}

	return 0;
}

int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access)
{
	struct trdc *trdc_base = (struct trdc *)0x28031000U;
	struct mrc_rgn_dom *mrc_dom;
	u32 *desc_w;
	u32 start, end;
	u32 i, free = 8;
	bool vld, hit = false;

	mrc_dom = &trdc_base->mrc_dom[mrc_x][dom_x];

	for (i = 0; i < 8; i++) {
		desc_w = &mrc_dom->rgn_desc_words[i][0];

		start = readl((void __iomem *)desc_w) & 0xfff;
		end = readl((void __iomem *)(desc_w + 1));
		vld = end & 0x1;
		end = end & 0xfff;

		if (start == 0 && end == 0 && !vld && free >= 8)
			free = i;

		/* Check all the region descriptors, even overlap */
		if (addr_start >= end || addr_end <= start || !vld)
			continue;

		/* MRC0,1
		 *  Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
		 *  So select MRCx_MEMN_GLBAC0
		 */
		if (sec_access) {
			writel(start, (void __iomem *)desc_w);
			writel(end | 0x1, (void __iomem *)(desc_w + 1));
		} else {
			writel(start, (void __iomem *)desc_w);
			writel((end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
		}

		if (addr_start >= start && addr_end <= end)
			hit = true;
	}

	if (!hit) {
		if (free >= 8)
			return -EFAULT;

		desc_w = &mrc_dom->rgn_desc_words[free][0];

		addr_start &= ~0xfff;
		addr_end &= ~0xfff;

		if (sec_access) {
			writel(addr_start, (void __iomem *)desc_w);
			writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
		} else {
			writel(addr_start, (void __iomem *)desc_w);
			writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
		}
	}

	return 0;
}
Commit	Line	Data
367ff4bc PF	1	// SPDX-License-Identifier: GPL-2.0+
367ff4bc PF	2	/*
3912d4b2	3	* Copyright 2021 NXP
367ff4bc PF	4	*/
367ff4bc PF	5
d678a59d	6	#include <common.h>
367ff4bc	7	#include <asm/io.h>
3912d4b2 PF	8	#include <asm/types.h>
3912d4b2 PF	9	#include <asm/arch/imx-regs.h>
367ff4bc	10	#include <asm/arch/sys_proto.h>
03fcf966	11	#include <asm/mach-imx/mu_hal.h>
d3ee9dbd	12	#include <asm/mach-imx/ele_api.h>
3912d4b2 PF	13	#include <asm/arch/rdc.h>
3912d4b2 PF	14	#include <div64.h>
367ff4bc PF	15
	16	#define XRDC_ADDR 0x292f0000
	17	#define MRC_OFFSET 0x2000
	18	#define MRC_STEP 0x200
	19
	20	#define SP(X) ((X) << 9)
	21	#define SU(X) ((X) << 6)
	22	#define NP(X) ((X) << 3)
	23	#define NU(X) ((X) << 0)
	24
	25	#define RWX 7
	26	#define RW 6
	27	#define R 4
	28	#define X 1
	29
	30	#define D7SEL_CODE (SP(RW) \| SU(RW) \| NP(RWX) \| NU(RWX))
	31	#define D6SEL_CODE (SP(RW) \| SU(RW) \| NP(RWX))
	32	#define D5SEL_CODE (SP(RW) \| SU(RWX))
	33	#define D4SEL_CODE SP(RWX)
	34	#define D3SEL_CODE (SP(X) \| SU(X) \| NP(X) \| NU(X))
	35	#define D0SEL_CODE 0
	36
	37	#define D7SEL_DAT (SP(RW) \| SU(RW) \| NP(RW) \| NU(RW))
	38	#define D6SEL_DAT (SP(RW) \| SU(RW) \| NP(RW))
	39	#define D5SEL_DAT (SP(RW) \| SU(RW) \| NP(R) \| NU(R))
	40	#define D4SEL_DAT (SP(RW) \| SU(RW))
	41	#define D3SEL_DAT SP(RW)
	42
3912d4b2 PF	43	struct mbc_mem_dom {
	44	u32 mem_glbcfg[4];
	45	u32 nse_blk_index;
	46	u32 nse_blk_set;
	47	u32 nse_blk_clr;
	48	u32 nsr_blk_clr_all;
	49	u32 memn_glbac[8];
	50	/* The upper only existed in the beginning of each MBC */
	51	u32 mem0_blk_cfg_w[64];
	52	u32 mem0_blk_nse_w[16];
	53	u32 mem1_blk_cfg_w[8];
	54	u32 mem1_blk_nse_w[2];
	55	u32 mem2_blk_cfg_w[8];
	56	u32 mem2_blk_nse_w[2];
	57	u32 mem3_blk_cfg_w[8];
	58	u32 mem3_blk_nse_w[2];/0x1F0, 0x1F4 /
	59	u32 reserved[2];
	60	};
	61
	62	struct mrc_rgn_dom {
	63	u32 mrc_glbcfg[4];
	64	u32 nse_rgn_indirect;
	65	u32 nse_rgn_set;
	66	u32 nse_rgn_clr;
	67	u32 nse_rgn_clr_all;
	68	u32 memn_glbac[8];
	69	/* The upper only existed in the beginning of each MRC */
	70	u32 rgn_desc_words[8][2]; /* 8 regions, 2 words per region */
	71	u32 reserved[16];
	72	u32 rgn_nse;
	73	u32 reserved2[15];
	74	};
	75
	76	struct trdc {
	77	u8 res0[0x1000];
	78	struct mbc_mem_dom mem_dom[4][8];
	79	struct mrc_rgn_dom mrc_dom[2][8];
	80	};
	81
367ff4bc PF	82	union dxsel_perm {
	83	struct {
	84	u8 dx;
	85	u8 perm;
	86	};
	87
	88	u32 dom_perm;
	89	};
	90
	91	int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel)
	92	{
	93	ulong w2_addr;
	94	u32 val = 0;
	95
	96	w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8;
	97
	98	val = (readl(w2_addr) & (~(7 << (3 * dom)))) \| (dxsel << (3 * dom));
	99	writel(val, w2_addr);
	100
	101	return 0;
	102	}
	103
	104	int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size)
	105	{
	106	ulong w0_addr, w1_addr;
	107
	108	w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
	109	w1_addr = w0_addr + 4;
	110
	111	if ((size % 32) != 0)
	112	return -EINVAL;
	113
	114	writel(w0 & ~0x1f, w0_addr);
	115	writel(w0 + size - 1, w1_addr);
	116
	117	return 0;
	118	}
	119
	120	int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4)
	121	{
	122	ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC;
	123	ulong w4_addr = w3_addr + 4;
	124
	125	writel(w3, w3_addr);
	126	writel(w4, w4_addr);
	127
	128	return 0;
	129	}
	130
	131	int xrdc_config_pdac_openacc(u32 bridge, u32 index)
	132	{
	133	ulong w0_addr;
	134	u32 val;
	135
	136	switch (bridge) {
	137	case 3:
	138	w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
	139	break;
	140	case 4:
	141	w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
	142	break;
	143	case 5:
	144	w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
	145	break;
146	default:
147	return -EINVAL;
148	}
149	writel(0xffffff, w0_addr);
150
151	val = readl(w0_addr + 4);
152	writel(val \| BIT(31), w0_addr + 4);
153
154	return 0;
155	}
156
157	int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
158	{
159	ulong w0_addr;
160	u32 val;
161
162	switch (bridge) {
163	case 3:
164	w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
165	break;
166	case 4:
167	w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
168	break;
169	case 5:
170	w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
171	break;
172	default:
173	return -EINVAL;
174	}
175	val = readl(w0_addr);
176	writel((val & ~(0x7 << (dom * 3))) \| (perm << (dom * 3)), w0_addr);
177
178	val = readl(w0_addr + 4);
179	writel(val \| BIT(31), w0_addr + 4);
180
181	return 0;
182	}
3912d4b2	183
cf352902 YL	184	int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
	185	{
	186	ulong w0_addr;
	187	u32 val;
	188
	189	if (msc > 2)
	190	return -EINVAL;
	191
	192	w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
	193
	194	val = readl(w0_addr);
	195	writel((val & ~(0x7 << (dom * 3))) \| (perm << (dom * 3)), w0_addr);
	196
	197	val = readl(w0_addr + 4);
	198	writel(val \| BIT(31), w0_addr + 4);
	199
	200	return 0;
	201	}
	202
3912d4b2 PF	203	int release_rdc(enum rdc_type type)
	204	{
	205	ulong s_mu_base = 0x27020000UL;
d3ee9dbd	206	struct ele_msg msg;
3912d4b2 PF	207	int ret;
	208	u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
	209
d3ee9dbd PF	210	msg.version = ELE_VERSION;
d3ee9dbd PF	211	msg.tag = ELE_CMD_TAG;
3912d4b2	212	msg.size = 2;
040fc2be	213	msg.command = ELE_RELEASE_RDC_REQ;
3912d4b2 PF	214	msg.data[0] = (rdc_id << 8) \| 0x2; /* A35 XRDC */
	215
	216	mu_hal_init(s_mu_base);
	217	mu_hal_sendmsg(s_mu_base, 0, ((u32 )&msg));
	218	mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
	219
	220	ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
	221	if (!ret) {
	222	ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
	223	if (!ret) {
	224	if ((msg.data[0] & 0xff) == 0xd6)
	225	return 0;
	226	}
	227
	228	return -EIO;
	229	}
	230
	231	return ret;
	232	}
	233
	234	void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
	235	{
	236	ulong xrdc_base = 0x292f0000, off;
	237	u32 mrgd[5];
	238	u8 mrcfg, j, region_num;
	239	u8 dsel;
	240
	241	mrcfg = readb(xrdc_base + 0x140 + mrc_index);
	242	region_num = mrcfg & 0x1f;
	243
	244	for (j = 0; j < region_num; j++) {
	245	off = 0x2000 + mrc_index * 0x200 + j * 0x20;
	246
	247	mrgd[0] = readl(xrdc_base + off);
	248	mrgd[1] = readl(xrdc_base + off + 4);
	249	mrgd[2] = readl(xrdc_base + off + 8);
	250	mrgd[3] = readl(xrdc_base + off + 0xc);
	251	mrgd[4] = readl(xrdc_base + off + 0x10);
	252
	253	debug("MRC [%u][%u]\n", mrc_index, j);
	254	debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
	255	mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]);
	256
	257	/* hit */
	258	if (addr >= mrgd[0] && addr <= mrgd[1]) {
	259	/* find domain 7 DSEL */
	260	dsel = (mrgd[2] >> 21) & 0x7;
	261	if (dsel == 1) {
	262	mrgd[4] &= ~0xFFF;
	263	mrgd[4] \|= (access & 0xFFF);
	264	} else if (dsel == 2) {
	265	mrgd[4] &= ~0xFFF0000;
	266	mrgd[4] \|= ((access & 0xFFF) << 16);
	267	}
	268
d3ee9dbd	269	/* not handle other cases, since ELE only set ACCESS1 and 2 */
3912d4b2 PF	270	writel(mrgd[4], xrdc_base + off + 0x10);
	271	return;
	272	}
	273	}
	274	}
	275
	276	void xrdc_init_mda(void)
	277	{
	278	ulong xrdc_base = XRDC_ADDR, off;
	279	u32 i = 0;
	280
	281	/* Set MDA3-5 for PXP, ENET, CAAM to DID 1*/
	282	for (i = 3; i <= 5; i++) {
	283	off = 0x800 + i * 0x20;
	284	writel(0x200000A1, xrdc_base + off);
	285	writel(0xA00000A1, xrdc_base + off);
	286	}
	287
	288	/* Set MDA10 -15 to DID 3 for video */
	289	for (i = 10; i <= 15; i++) {
	290	off = 0x800 + i * 0x20;
	291	writel(0x200000A3, xrdc_base + off);
	292	writel(0xA00000A3, xrdc_base + off);
	293	}
	294	}
	295
	296	void xrdc_init_mrc(void)
	297	{
d3ee9dbd	298	/* Re-config MRC3 for SRAM0 in case protected by ELE */
e01d1b1e YL	299	xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
	300	xrdc_config_mrc_dx_perm(3, 0, 0, 1);
	301	xrdc_config_mrc_dx_perm(3, 0, 1, 1);
	302	xrdc_config_mrc_dx_perm(3, 0, 4, 1);
	303	xrdc_config_mrc_dx_perm(3, 0, 5, 1);
	304	xrdc_config_mrc_dx_perm(3, 0, 6, 1);
	305	xrdc_config_mrc_dx_perm(3, 0, 7, 1);
	306	xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF);
	307
	308	/* Clear other 3 regions of MRC3 to invalid */
	309	xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0);
	310	xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0);
	311	xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0);
	312
237ce9b6 YL	313	/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
	314	xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
	315	xrdc_config_mrc_dx_perm(4, 0, 1, 1);
	316	xrdc_config_mrc_dx_perm(4, 0, 7, 1);
	317	xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
	318
	319	xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
	320	xrdc_config_mrc_dx_perm(5, 0, 1, 1);
	321	xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
	322
d3ee9dbd	323	/* Set MRC6 for DDR access from ELE */
84f7da68 YL	324	xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
	325	xrdc_config_mrc_dx_perm(6, 0, 4, 1);
	326	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
	327
3912d4b2 PF	328	/* The MRC8 is for SRAM1 */
	329	xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
	330	/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
	331	xrdc_config_mrc_dx_perm(8, 0, 0, 1);
	332	xrdc_config_mrc_dx_perm(8, 0, 1, 1);
	333	xrdc_config_mrc_dx_perm(8, 0, 2, 1);
	334	xrdc_config_mrc_dx_perm(8, 0, 3, 1);
	335	xrdc_config_mrc_dx_perm(8, 0, 4, 1);
	336	xrdc_config_mrc_dx_perm(8, 0, 5, 1);
	337	xrdc_config_mrc_dx_perm(8, 0, 6, 1);
	338	xrdc_config_mrc_dx_perm(8, 0, 7, 1);
	339	xrdc_config_mrc_w3_w4(8, 0, 0x0, 0x80000FFF);
	340
	341	/* The MRC6 is for video modules to ddr */
	342	xrdc_config_mrc_w0_w1(6, 0, 0x80000000, 0x80000000);
	343	xrdc_config_mrc_dx_perm(6, 0, 3, 1); /* allow for domain 3 video */
	344	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
	345	}
	346
cf352902 YL	347	void xrdc_init_pdac_msc(void)
	348	{
	349	/* Init LPAV PDAC and MSC for DDR init */
	350	xrdc_config_pdac(5, 36, 6, 0x7); /* CMC2*/
	351	xrdc_config_pdac(5, 36, 7, 0x7);
	352	xrdc_config_pdac(5, 37, 6, 0x7); /* SIM2 */
	353	xrdc_config_pdac(5, 37, 7, 0x7);
	354	xrdc_config_pdac(5, 38, 6, 0x7); /* CGC2 */
	355	xrdc_config_pdac(5, 38, 7, 0x7);
	356	xrdc_config_pdac(5, 39, 6, 0x7); /* PCC5 */
	357	xrdc_config_pdac(5, 39, 7, 0x7);
	358
	359	xrdc_config_msc(0, 0, 6, 0x7); /* GPIOE */
	360	xrdc_config_msc(0, 0, 7, 0x7);
	361	xrdc_config_msc(0, 1, 6, 0x7); /* GPIOF */
	362	xrdc_config_msc(0, 1, 7, 0x7);
	363	xrdc_config_msc(1, 0, 6, 0x7); /* GPIOD */
	364	xrdc_config_msc(1, 0, 7, 0x7);
	365	xrdc_config_msc(2, 6, 6, 0x7); /* DDR controller */
	366	xrdc_config_msc(2, 6, 7, 0x7);
	367	}
	368
3912d4b2 PF	369	int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access)
	370	{
	371	struct trdc trdc_base = (struct trdc )0x28031000U;
	372	struct mbc_mem_dom *mbc_dom;
	373	u32 cfg_w, nse_w;
	374	u32 index, offset, val;
	375
	376	mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x];
	377
	378	switch (mem_x) {
	379	case 0:
	380	cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
	381	nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
	382	break;
	383	case 1:
	384	cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
	385	nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
	386	break;
	387	case 2:
	388	cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
	389	nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
	390	break;
	391	case 3:
	392	cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
	393	nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
	394	break;
	395	default:
	396	return -EINVAL;
	397	};
	398
	399	index = blk_x % 8;
	400	offset = index * 4;
	401
	402	val = readl((void __iomem *)cfg_w);
	403
	404	val &= ~(0xFU << offset);
	405
	406	/* MBC0-3
d3ee9dbd	407	* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
3912d4b2 PF	408	* So select MBC0_MEMN_GLBAC0
	409	*/
	410	if (sec_access) {
	411	val \|= (0x0 << offset);
	412	writel(val, (void __iomem *)cfg_w);
	413	} else {
	414	val \|= (0x8 << offset); /* nse bit set */
	415	writel(val, (void __iomem *)cfg_w);
	416	}
	417
	418	return 0;
	419	}
	420
	421	int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access)
	422	{
	423	struct trdc trdc_base = (struct trdc )0x28031000U;
	424	struct mrc_rgn_dom *mrc_dom;
	425	u32 *desc_w;
	426	u32 start, end;
	427	u32 i, free = 8;
	428	bool vld, hit = false;
	429
	430	mrc_dom = &trdc_base->mrc_dom[mrc_x][dom_x];
	431
	432	for (i = 0; i < 8; i++) {
	433	desc_w = &mrc_dom->rgn_desc_words[i][0];
	434
	435	start = readl((void __iomem *)desc_w) & 0xfff;
	436	end = readl((void __iomem *)(desc_w + 1));
	437	vld = end & 0x1;
	438	end = end & 0xfff;
	439
	440	if (start == 0 && end == 0 && !vld && free >= 8)
	441	free = i;
	442
	443	/* Check all the region descriptors, even overlap */
	444	if (addr_start >= end \|\| addr_end <= start \|\| !vld)
	445	continue;
	446
	447	/* MRC0,1
d3ee9dbd	448	* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
3912d4b2 PF	449	* So select MRCx_MEMN_GLBAC0
	450	*/
	451	if (sec_access) {
	452	writel(start, (void __iomem *)desc_w);
	453	writel(end \| 0x1, (void __iomem *)(desc_w + 1));
	454	} else {
	455	writel(start, (void __iomem *)desc_w);
	456	writel((end \| 0x1 \| 0x10), (void __iomem *)(desc_w + 1));
	457	}
	458
	459	if (addr_start >= start && addr_end <= end)
	460	hit = true;
	461	}
	462
	463	if (!hit) {
	464	if (free >= 8)
	465	return -EFAULT;
	466
	467	desc_w = &mrc_dom->rgn_desc_words[free][0];
	468
	469	addr_start &= ~0xfff;
	470	addr_end &= ~0xfff;
	471
	472	if (sec_access) {
	473	writel(addr_start, (void __iomem *)desc_w);
	474	writel(addr_end \| 0x1, (void __iomem *)(desc_w + 1));
	475	} else {
	476	writel(addr_start, (void __iomem *)desc_w);
	477	writel((addr_end \| 0x1 \| 0x10), (void __iomem *)(desc_w + 1));
	478	}
	479	}
	480
	481	return 0;
	482	}