[thirdparty/u-boot.git] / arch / arm / mach-imx / mx7 / soc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 * Copyright 2021 NXP
 */

#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/dma.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
#include <asm/setup.h>
#include <linux/delay.h>

#define IOMUXC_GPR1		0x4
#define BM_IOMUXC_GPR1_IRQ	0x1000

#define GPC_LPCR_A7_BSC		0x0
#define GPC_LPCR_M4		0x8
#define GPC_SLPCR		0x14
#define GPC_PGC_ACK_SEL_A7	0x24
#define GPC_IMR1_CORE0		0x30
#define GPC_IMR1_CORE1		0x40
#define GPC_IMR1_M4		0x50
#define GPC_PGC_CPU_MAPPING	0xec
#define GPC_PGC_C0_PUPSCR	0x804
#define GPC_PGC_SCU_TIMING	0x890
#define GPC_PGC_C1_PUPSCR	0x844

#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP	0x70000000
#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM		0x4000
#define BM_LPCR_M4_MASK_DSM_TRIGGER		0x80000000
#define BM_SLPCR_EN_DSM				0x80000000
#define BM_SLPCR_RBC_EN				0x40000000
#define BM_SLPCR_REG_BYPASS_COUNT		0x3f000000
#define BM_SLPCR_VSTBY				0x4
#define BM_SLPCR_SBYOS				0x2
#define BM_SLPCR_BYPASS_PMIC_READY		0x1
#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE	0x10000

#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK	0x80000000
#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK	0x8000

#define BM_GPC_PGC_CORE_PUPSCR			0x7fff80

#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx7_thermal_plat = {
	.regs = (void *)ANATOP_BASE_ADDR,
	.fuse_bank = 3,
	.fuse_word = 3,
};

U_BOOT_DRVINFO(imx7_thermal) = {
	.name = "imx_thermal",
	.plat = &imx7_thermal_plat,
};
#endif

#if CONFIG_IS_ENABLED(IMX_RDC)
/*
 * In current design, if any peripheral was assigned to both A7 and M4,
 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
 * low power mode. So M4 sleep will cause some peripherals fail to work
 * at A7 core side. At default, all resources are in domain 0 - 3.
 *
 * There are 26 peripherals impacted by this IC issue:
 * SIM2(sim2/emvsim2)
 * SIM1(sim1/emvsim1)
 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
 * SAI1/SAI2/SAI3
 * WDOG1/WDOG2/WDOG3/WDOG4
 * GPT1/GPT2/GPT3/GPT4
 * PWM1/PWM2/PWM3/PWM4
 * ENET1/ENET2
 * Software Workaround:
 * Here we setup some resources to domain 0 where M4 codes will move
 * the M4 out of this domain. Then M4 is not able to access them any longer.
 * This is a workaround for ic issue. So the peripherals are not shared
 * by them. This way requires the uboot implemented the RDC driver and
 * set the 26 IPs above to domain 0 only. M4 code will assign resource
 * to its own domain, if it want to use the resource.
 */
static rdc_peri_cfg_t const resources[] = {
	(RDC_PER_SIM1 | RDC_DOMAIN(0)),
	(RDC_PER_SIM2 | RDC_DOMAIN(0)),
	(RDC_PER_UART1 | RDC_DOMAIN(0)),
	(RDC_PER_UART2 | RDC_DOMAIN(0)),
	(RDC_PER_UART3 | RDC_DOMAIN(0)),
	(RDC_PER_UART4 | RDC_DOMAIN(0)),
	(RDC_PER_UART5 | RDC_DOMAIN(0)),
	(RDC_PER_UART6 | RDC_DOMAIN(0)),
	(RDC_PER_UART7 | RDC_DOMAIN(0)),
	(RDC_PER_SAI1 | RDC_DOMAIN(0)),
	(RDC_PER_SAI2 | RDC_DOMAIN(0)),
	(RDC_PER_SAI3 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
	(RDC_PER_GPT1 | RDC_DOMAIN(0)),
	(RDC_PER_GPT2 | RDC_DOMAIN(0)),
	(RDC_PER_GPT3 | RDC_DOMAIN(0)),
	(RDC_PER_GPT4 | RDC_DOMAIN(0)),
	(RDC_PER_PWM1 | RDC_DOMAIN(0)),
	(RDC_PER_PWM2 | RDC_DOMAIN(0)),
	(RDC_PER_PWM3 | RDC_DOMAIN(0)),
	(RDC_PER_PWM4 | RDC_DOMAIN(0)),
	(RDC_PER_ENET1 | RDC_DOMAIN(0)),
	(RDC_PER_ENET2 | RDC_DOMAIN(0)),
};

static void isolate_resource(void)
{
	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
}
#endif

#if defined(CONFIG_IMX_HAB)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	.bank = 1,
	.word = 3,
};
#endif

static bool is_mx7d(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	int val;

	val = readl(&fuse->tester4);
	if (val & 1)
		return false;
	else
		return true;
}

u32 get_cpu_rev(void)
{
	struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
						 ANATOP_BASE_ADDR;
	u32 reg = readl(&ccm_anatop->digprog);
	u32 type = (reg >> 16) & 0xff;

	if (!is_mx7d())
		type = MXC_CPU_MX7S;

	reg &= 0xff;
	return (type << 12) | reg;
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	return get_cpu_rev();
}
#endif

static void imx_enet_mdio_fixup(void)
{
	struct iomuxc_gpr_base_regs *gpr_regs =
		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

	/*
	 * The management data input/output (MDIO) requires open-drain,
	 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
	 * this feature. So to TO1.1, need to enable open drain by setting
	 * bits GPR0[8:7].
	 */

	if (soc_rev() >= CHIP_REV_1_1) {
		setbits_le32(&gpr_regs->gpr[0],
			     IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
	}
}

static void init_cpu_basic(void)
{
	imx_enet_mdio_fixup();

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif
}

#ifdef CONFIG_IMX_BOOTAUX
/*
 * Table of mappings of physical mem regions in both
 * Cortex-A7 and Cortex-M4 address spaces.
 *
 * For additional details check sections 2.1.2 and 2.1.3 in
 * i.MX7Dual Applications Processor Reference Manual
 *
 */
const struct rproc_att hostmap[] = {
	/* aux core , host core,  size */
	{ 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
	{ 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
	{ 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
	{ 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
	{ 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
	{ 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
	{ 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
	{ 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
	{ 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
	{ 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
	{ 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
	{ 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
	{ 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
	{ /* sentinel */ }
};

const struct rproc_att *imx_bootaux_get_hostmap(void)
{
	return hostmap;
}
#endif

#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* enable all periherial can be accessed in nosec mode */
static void init_csu(void)
{
	int i = 0;

	for (i = 0; i < CSU_NUM_REGS; i++)
		writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}

static void imx_gpcv2_init(void)
{
	u32 val, i;

	/*
	 * Force IOMUXC irq pending, so that the interrupt to GPC can be
	 * used to deassert dsm_request signal when the signal gets
	 * asserted unexpectedly.
	 */
	val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
	val |= BM_IOMUXC_GPR1_IRQ;
	writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);

	/* Initially mask all interrupts */
	for (i = 0; i < 4; i++) {
		writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
		writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
		writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
	}

	/* set SCU timing */
	writel((0x59 << 10) | 0x5B | (0x2 << 20),
	       GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);

	/* only external IRQs to wake up LPM and core 0/1 */
	val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
	val |= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
	writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);

	/* set C0 power up timming per design requirement */
	val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
	val &= ~BM_GPC_PGC_CORE_PUPSCR;
	val |= (0x1A << 7);
	writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);

	/* set C1 power up timming per design requirement */
	val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
	val &= ~BM_GPC_PGC_CORE_PUPSCR;
	val |= (0x1A << 7);
	writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);

	/* dummy ack for time slot by default */
	writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK |
		BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
		GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);

	/* mask M4 DSM trigger */
	writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) |
		 BM_LPCR_M4_MASK_DSM_TRIGGER,
		 GPC_IPS_BASE_ADDR + GPC_LPCR_M4);

	/* set mega/fast mix in A7 domain */
	writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);

	/* DSM related settings */
	val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
	val &= ~(BM_SLPCR_EN_DSM | BM_SLPCR_VSTBY | BM_SLPCR_RBC_EN |
		BM_SLPCR_SBYOS | BM_SLPCR_BYPASS_PMIC_READY |
		BM_SLPCR_REG_BYPASS_COUNT);
	val |= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
	writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);

	/*
	 * disabling RBC need to delay at least 2 cycles of CKIL(32K)
	 * due to hardware design requirement, which is
	 * ~61us, here we use 65us for safe
	 */
	udelay(65);
}

int arch_cpu_init(void)
{
	init_aips();

	init_csu();
	/* Disable PDE bit of WMCR register */
	imx_wdog_disable_powerdown();

	init_cpu_basic();

#if CONFIG_IS_ENABLED(IMX_RDC)
	isolate_resource();
#endif

	init_snvs();

	imx_gpcv2_init();

	enable_ca7_smp();

	return 0;
}
#else
int arch_cpu_init(void)
{
	init_cpu_basic();

	return 0;
}
#endif

#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	struct tag_serialnr serialnr;
	char serial_string[0x20];

	if (is_mx7d())
		env_set("soc", "imx7d");
	else
		env_set("soc", "imx7s");

	/* Set serial# standard environment variable based on OTP settings */
	get_board_serial(&serialnr);
	snprintf(serial_string, sizeof(serial_string), "0x%08x%08x",
		 serialnr.low, serialnr.high);
	env_set("serial#", serial_string);
#endif

	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
		struct udevice *dev;
		int ret;
		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
		if (ret)
			printf("Failed to initialize caam_jr: %d\n", ret);
	}

	return 0;
}
#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/*
 * OCOTP_TESTER
 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
 * OCOTP_TESTER describes a unique ID based on silicon wafer
 * and die X/Y position
 *
 * OCOTOP_TESTER offset 0x410
 * 31:0 fuse 0
 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
 *
 * OCOTP_TESTER1 offset 0x420
 * 31:24 fuse 1
 * The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
 * 23:16 fuse 1
 * The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
 * 15:11 fuse 1
 * The wafer number of the wafer on which the device was fabricated/SJC
 * CHALLENGE/ Unique ID
 * 10:0 fuse 1
 * FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
 */
void get_board_serial(struct tag_serialnr *serialnr)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[0];
	struct fuse_bank0_regs *fuse =
		(struct fuse_bank0_regs *)bank->fuse_regs;

	serialnr->low = fuse->tester0;
	serialnr->high = fuse->tester1;
}
#endif

void set_wdog_reset(struct wdog_regs *wdog)
{
	u32 reg = readw(&wdog->wcr);
	/*
	 * Output WDOG_B signal to reset external pmic or POR_B decided by
	 * the board desgin. Without external reset, the peripherals/DDR/
	 * PMIC are not reset, that may cause system working abnormal.
	 */
	reg = readw(&wdog->wcr);
	reg |= 1 << 3;
	/*
	 * WDZST bit is write-once only bit. Align this bit in kernel,
	 * otherwise kernel code will have no chance to set this bit.
	 */
	reg |= 1 << 0;
	writew(reg, &wdog->wcr);
}

void s_init(void)
{
	/* clock configuration. */
	clock_init();

	return;
}

#ifndef CONFIG_SPL_BUILD
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	{"primary",	MAKE_CFGVAL_PRIMARY_BOOT},
	{"secondary",	MAKE_CFGVAL_SECONDARY_BOOT},
	{NULL,		0},
};

int boot_mode_getprisec(void)
{
	struct src *psrc = (struct src *)SRC_BASE_ADDR;

	return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
}
#endif

void reset_misc(void)
{
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
	lcdif_power_down();
#endif
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c5752f73 AA	2	/*
c5752f73 AA	3	* Copyright (C) 2015 Freescale Semiconductor, Inc.
4f1375d4	4	* Copyright 2021 NXP
c5752f73 AA	5	*/
c5752f73 AA	6
d678a59d	7	#include <common.h>
691d719d	8	#include <init.h>
c5752f73 AA	9	#include <asm/io.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/clock.h>
	12	#include <asm/arch/sys_proto.h>
552a848e SB	13	#include <asm/mach-imx/dma.h>
	14	#include <asm/mach-imx/hab.h>
	15	#include <asm/mach-imx/rdc-sema.h>
35c4ce5e	16	#include <asm/arch/imx-rdc.h>
c72372d3	17	#include <asm/mach-imx/boot_mode.h>
0be742d0	18	#include <asm/mach-imx/sys_proto.h>
c5752f73	19	#include <asm/arch/crm_regs.h>
b9d66a06	20	#include <asm/bootm.h>
c5752f73	21	#include <dm.h>
9fb625ce	22	#include <env.h>
c5752f73	23	#include <imx_thermal.h>
ca831822	24	#include <asm/setup.h>
c05ed00a	25	#include <linux/delay.h>
c5752f73	26
b0598378 AH	27	#define IOMUXC_GPR1 0x4
	28	#define BM_IOMUXC_GPR1_IRQ 0x1000
	29
	30	#define GPC_LPCR_A7_BSC 0x0
	31	#define GPC_LPCR_M4 0x8
	32	#define GPC_SLPCR 0x14
	33	#define GPC_PGC_ACK_SEL_A7 0x24
	34	#define GPC_IMR1_CORE0 0x30
	35	#define GPC_IMR1_CORE1 0x40
	36	#define GPC_IMR1_M4 0x50
	37	#define GPC_PGC_CPU_MAPPING 0xec
	38	#define GPC_PGC_C0_PUPSCR 0x804
	39	#define GPC_PGC_SCU_TIMING 0x890
	40	#define GPC_PGC_C1_PUPSCR 0x844
	41
	42	#define BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP 0x70000000
	43	#define BM_LPCR_A7_BSC_CPU_CLK_ON_LPM 0x4000
	44	#define BM_LPCR_M4_MASK_DSM_TRIGGER 0x80000000
	45	#define BM_SLPCR_EN_DSM 0x80000000
	46	#define BM_SLPCR_RBC_EN 0x40000000
	47	#define BM_SLPCR_REG_BYPASS_COUNT 0x3f000000
	48	#define BM_SLPCR_VSTBY 0x4
	49	#define BM_SLPCR_SBYOS 0x2
	50	#define BM_SLPCR_BYPASS_PMIC_READY 0x1
	51	#define BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE 0x10000
	52
	53	#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK 0x80000000
	54	#define BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK 0x8000
	55
	56	#define BM_GPC_PGC_CORE_PUPSCR 0x7fff80
	57
c5752f73 AA	58	#if defined(CONFIG_IMX_THERMAL)
	59	static const struct imx_thermal_plat imx7_thermal_plat = {
	60	.regs = (void *)ANATOP_BASE_ADDR,
	61	.fuse_bank = 3,
	62	.fuse_word = 3,
	63	};
	64
20e442ab	65	U_BOOT_DRVINFO(imx7_thermal) = {
c5752f73	66	.name = "imx_thermal",
caa4daa2	67	.plat = &imx7_thermal_plat,
c5752f73 AA	68	};
	69	#endif
	70
e872f27a	71	#if CONFIG_IS_ENABLED(IMX_RDC)
35c4ce5e PF	72	/*
	73	* In current design, if any peripheral was assigned to both A7 and M4,
	74	* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
	75	* low power mode. So M4 sleep will cause some peripherals fail to work
	76	* at A7 core side. At default, all resources are in domain 0 - 3.
	77	*
	78	* There are 26 peripherals impacted by this IC issue:
	79	* SIM2(sim2/emvsim2)
	80	* SIM1(sim1/emvsim1)
	81	* UART1/UART2/UART3/UART4/UART5/UART6/UART7
	82	* SAI1/SAI2/SAI3
	83	* WDOG1/WDOG2/WDOG3/WDOG4
	84	* GPT1/GPT2/GPT3/GPT4
	85	* PWM1/PWM2/PWM3/PWM4
	86	* ENET1/ENET2
	87	* Software Workaround:
	88	* Here we setup some resources to domain 0 where M4 codes will move
	89	* the M4 out of this domain. Then M4 is not able to access them any longer.
	90	* This is a workaround for ic issue. So the peripherals are not shared
	91	* by them. This way requires the uboot implemented the RDC driver and
	92	* set the 26 IPs above to domain 0 only. M4 code will assign resource
	93	* to its own domain, if it want to use the resource.
	94	*/
	95	static rdc_peri_cfg_t const resources[] = {
	96	(RDC_PER_SIM1 \| RDC_DOMAIN(0)),
	97	(RDC_PER_SIM2 \| RDC_DOMAIN(0)),
	98	(RDC_PER_UART1 \| RDC_DOMAIN(0)),
	99	(RDC_PER_UART2 \| RDC_DOMAIN(0)),
	100	(RDC_PER_UART3 \| RDC_DOMAIN(0)),
	101	(RDC_PER_UART4 \| RDC_DOMAIN(0)),
	102	(RDC_PER_UART5 \| RDC_DOMAIN(0)),
	103	(RDC_PER_UART6 \| RDC_DOMAIN(0)),
	104	(RDC_PER_UART7 \| RDC_DOMAIN(0)),
	105	(RDC_PER_SAI1 \| RDC_DOMAIN(0)),
	106	(RDC_PER_SAI2 \| RDC_DOMAIN(0)),
	107	(RDC_PER_SAI3 \| RDC_DOMAIN(0)),
	108	(RDC_PER_WDOG1 \| RDC_DOMAIN(0)),
	109	(RDC_PER_WDOG2 \| RDC_DOMAIN(0)),
	110	(RDC_PER_WDOG3 \| RDC_DOMAIN(0)),
	111	(RDC_PER_WDOG4 \| RDC_DOMAIN(0)),
	112	(RDC_PER_GPT1 \| RDC_DOMAIN(0)),
	113	(RDC_PER_GPT2 \| RDC_DOMAIN(0)),
	114	(RDC_PER_GPT3 \| RDC_DOMAIN(0)),
	115	(RDC_PER_GPT4 \| RDC_DOMAIN(0)),
	116	(RDC_PER_PWM1 \| RDC_DOMAIN(0)),
	117	(RDC_PER_PWM2 \| RDC_DOMAIN(0)),
	118	(RDC_PER_PWM3 \| RDC_DOMAIN(0)),
	119	(RDC_PER_PWM4 \| RDC_DOMAIN(0)),
	120	(RDC_PER_ENET1 \| RDC_DOMAIN(0)),
	121	(RDC_PER_ENET2 \| RDC_DOMAIN(0)),
	122	};
	123
	124	static void isolate_resource(void)
	125	{
	126	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
	127	}
	128	#endif
	129
d714a75f	130	#if defined(CONFIG_IMX_HAB)
bb955146 AA	131	struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	132	.bank = 1,
	133	.word = 3,
	134	};
	135	#endif
	136
e25a0656 FE	137	static bool is_mx7d(void)
	138	{
	139	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	140	struct fuse_bank *bank = &ocotp->bank[1];
	141	struct fuse_bank1_regs *fuse =
	142	(struct fuse_bank1_regs *)bank->fuse_regs;
	143	int val;
	144
	145	val = readl(&fuse->tester4);
	146	if (val & 1)
	147	return false;
	148	else
	149	return true;
	150	}
	151
c5752f73 AA	152	u32 get_cpu_rev(void)
	153	{
	154	struct mxc_ccm_anatop_reg ccm_anatop = (struct mxc_ccm_anatop_reg )
	155	ANATOP_BASE_ADDR;
	156	u32 reg = readl(&ccm_anatop->digprog);
	157	u32 type = (reg >> 16) & 0xff;
	158
e25a0656 FE	159	if (!is_mx7d())
	160	type = MXC_CPU_MX7S;
	161
c5752f73 AA	162	reg &= 0xff;
	163	return (type << 12) \| reg;
	164	}
	165
	166	#ifdef CONFIG_REVISION_TAG
	167	u32 __weak get_board_rev(void)
	168	{
	169	return get_cpu_rev();
	170	}
	171	#endif
	172
d9699de8 PF	173	static void imx_enet_mdio_fixup(void)
	174	{
	175	struct iomuxc_gpr_base_regs *gpr_regs =
	176	(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	177
	178	/*
	179	* The management data input/output (MDIO) requires open-drain,
	180	* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
	181	* this feature. So to TO1.1, need to enable open drain by setting
	182	* bits GPR0[8:7].
	183	*/
	184
	185	if (soc_rev() >= CHIP_REV_1_1) {
	186	setbits_le32(&gpr_regs->gpr[0],
	187	IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
	188	}
	189	}
	190
bc7c9ed3 JN	191	static void init_cpu_basic(void)
	192	{
	193	imx_enet_mdio_fixup();
	194
	195	#ifdef CONFIG_APBH_DMA
	196	/* Start APBH DMA */
	197	mxs_dma_init();
	198	#endif
	199	}
	200
c0f037f6 IO	201	#ifdef CONFIG_IMX_BOOTAUX
	202	/*
	203	* Table of mappings of physical mem regions in both
	204	* Cortex-A7 and Cortex-M4 address spaces.
	205	*
	206	* For additional details check sections 2.1.2 and 2.1.3 in
	207	* i.MX7Dual Applications Processor Reference Manual
	208	*
	209	*/
	210	const struct rproc_att hostmap[] = {
	211	/* aux core , host core, size */
	212	{ 0x00000000, 0x00180000, 0x8000 }, /* OCRAM_S */
	213	{ 0x00180000, 0x00180000, 0x8000 }, /* OCRAM_S */
	214	{ 0x20180000, 0x00180000, 0x8000 }, /* OCRAM_S */
	215	{ 0x1fff8000, 0x007f8000, 0x8000 }, /* TCML */
	216	{ 0x20000000, 0x00800000, 0x8000 }, /* TCMU */
	217	{ 0x00900000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
	218	{ 0x20200000, 0x00900000, 0x20000 }, /* OCRAM_128KB */
	219	{ 0x00920000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
	220	{ 0x20220000, 0x00920000, 0x20000 }, /* OCRAM_EPDC */
	221	{ 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
	222	{ 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
	223	{ 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
fb99ac9c	224	{ 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
c0f037f6 IO	225	{ /* sentinel */ }
c0f037f6 IO	226	};
3f7afddc MV	227
	228	const struct rproc_att *imx_bootaux_get_hostmap(void)
	229	{
	230	return hostmap;
	231	}
c0f037f6 IO	232	#endif
c0f037f6 IO	233
a2ac2b96	234	#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bc7c9ed3 JN	235	/* enable all periherial can be accessed in nosec mode */
	236	static void init_csu(void)
	237	{
	238	int i = 0;
	239
	240	for (i = 0; i < CSU_NUM_REGS; i++)
	241	writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
	242	}
	243
b0598378 AH	244	static void imx_gpcv2_init(void)
	245	{
	246	u32 val, i;
	247
	248	/*
	249	* Force IOMUXC irq pending, so that the interrupt to GPC can be
	250	* used to deassert dsm_request signal when the signal gets
	251	* asserted unexpectedly.
	252	*/
	253	val = readl(IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
	254	val \|= BM_IOMUXC_GPR1_IRQ;
	255	writel(val, IOMUXC_GPR_BASE_ADDR + IOMUXC_GPR1);
	256
	257	/* Initially mask all interrupts */
	258	for (i = 0; i < 4; i++) {
	259	writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE0 + i * 4);
	260	writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_CORE1 + i * 4);
	261	writel(~0, GPC_IPS_BASE_ADDR + GPC_IMR1_M4 + i * 4);
	262	}
	263
	264	/* set SCU timing */
	265	writel((0x59 << 10) \| 0x5B \| (0x2 << 20),
	266	GPC_IPS_BASE_ADDR + GPC_PGC_SCU_TIMING);
	267
	268	/* only external IRQs to wake up LPM and core 0/1 */
	269	val = readl(GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
	270	val \|= BM_LPCR_A7_BSC_IRQ_SRC_A7_WAKEUP;
	271	writel(val, GPC_IPS_BASE_ADDR + GPC_LPCR_A7_BSC);
	272
	273	/* set C0 power up timming per design requirement */
	274	val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
	275	val &= ~BM_GPC_PGC_CORE_PUPSCR;
	276	val \|= (0x1A << 7);
	277	writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C0_PUPSCR);
	278
	279	/* set C1 power up timming per design requirement */
	280	val = readl(GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
	281	val &= ~BM_GPC_PGC_CORE_PUPSCR;
	282	val \|= (0x1A << 7);
	283	writel(val, GPC_IPS_BASE_ADDR + GPC_PGC_C1_PUPSCR);
	284
	285	/* dummy ack for time slot by default */
	286	writel(BM_GPC_PGC_ACK_SEL_A7_DUMMY_PUP_ACK \|
	287	BM_GPC_PGC_ACK_SEL_A7_DUMMY_PDN_ACK,
	288	GPC_IPS_BASE_ADDR + GPC_PGC_ACK_SEL_A7);
	289
	290	/* mask M4 DSM trigger */
	291	writel(readl(GPC_IPS_BASE_ADDR + GPC_LPCR_M4) \|
	292	BM_LPCR_M4_MASK_DSM_TRIGGER,
	293	GPC_IPS_BASE_ADDR + GPC_LPCR_M4);
	294
	295	/* set mega/fast mix in A7 domain */
	296	writel(0x1, GPC_IPS_BASE_ADDR + GPC_PGC_CPU_MAPPING);
	297
	298	/* DSM related settings */
	299	val = readl(GPC_IPS_BASE_ADDR + GPC_SLPCR);
	300	val &= ~(BM_SLPCR_EN_DSM \| BM_SLPCR_VSTBY \| BM_SLPCR_RBC_EN \|
	301	BM_SLPCR_SBYOS \| BM_SLPCR_BYPASS_PMIC_READY \|
	302	BM_SLPCR_REG_BYPASS_COUNT);
	303	val \|= BM_SLPCR_EN_A7_FASTWUP_WAIT_MODE;
	304	writel(val, GPC_IPS_BASE_ADDR + GPC_SLPCR);
	305
	306	/*
	307	* disabling RBC need to delay at least 2 cycles of CKIL(32K)
308	* due to hardware design requirement, which is
309	* ~61us, here we use 65us for safe
310	*/
311	udelay(65);
312	}
313
c5752f73 AA	314	int arch_cpu_init(void)
	315	{
	316	init_aips();
	317
7de47036	318	init_csu();
c5752f73	319	/* Disable PDE bit of WMCR register */
e2162d70	320	imx_wdog_disable_powerdown();
c5752f73	321
bc7c9ed3	322	init_cpu_basic();
c5752f73	323
e872f27a PF	324	#if CONFIG_IS_ENABLED(IMX_RDC)
	325	isolate_resource();
	326	#endif
35c4ce5e	327
723f8359 BD	328	init_snvs();
723f8359 BD	329
b0598378 AH	330	imx_gpcv2_init();
b0598378 AH	331
0be742d0 SS	332	enable_ca7_smp();
0be742d0 SS	333
c5752f73 AA	334	return 0;
c5752f73 AA	335	}
bc7c9ed3 JN	336	#else
	337	int arch_cpu_init(void)
	338	{
	339	init_cpu_basic();
	340
c5752f73 AA	341	return 0;
c5752f73 AA	342	}
be277c3a	343	#endif
c5752f73	344
ec7fde3e SA	345	#ifdef CONFIG_ARCH_MISC_INIT
	346	int arch_misc_init(void)
	347	{
	348	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
b9d66a06 TR	349	struct tag_serialnr serialnr;
	350	char serial_string[0x20];
	351
ec7fde3e	352	if (is_mx7d())
382bee57	353	env_set("soc", "imx7d");
ec7fde3e	354	else
382bee57	355	env_set("soc", "imx7s");
b9d66a06 TR	356
	357	/* Set serial# standard environment variable based on OTP settings */
	358	get_board_serial(&serialnr);
	359	snprintf(serial_string, sizeof(serial_string), "0x%08x%08x",
	360	serialnr.low, serialnr.high);
	361	env_set("serial#", serial_string);
ec7fde3e SA	362	#endif
ec7fde3e SA	363
4f1375d4 GJ	364	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
	365	struct udevice *dev;
	366	int ret;
	367	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
	368	if (ret)
cda8f873	369	printf("Failed to initialize caam_jr: %d\n", ret);
4f1375d4	370	}
d1ceb0c4	371
ec7fde3e SA	372	return 0;
	373	}
	374	#endif
	375
b9d66a06	376	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
1ab1ffde BD	377	/*
	378	* OCOTP_TESTER
	379	* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
	380	* OCOTP_TESTER describes a unique ID based on silicon wafer
	381	* and die X/Y position
	382	*
	383	* OCOTOP_TESTER offset 0x410
	384	* 31:0 fuse 0
	385	* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
	386	*
	387	* OCOTP_TESTER1 offset 0x420
	388	* 31:24 fuse 1
	389	* The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
	390	* 23:16 fuse 1
	391	* The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
	392	* 15:11 fuse 1
	393	* The wafer number of the wafer on which the device was fabricated/SJC
	394	* CHALLENGE/ Unique ID
	395	* 10:0 fuse 1
	396	* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
	397	*/
c5752f73 AA	398	void get_board_serial(struct tag_serialnr *serialnr)
	399	{
	400	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	401	struct fuse_bank *bank = &ocotp->bank[0];
	402	struct fuse_bank0_regs *fuse =
	403	(struct fuse_bank0_regs *)bank->fuse_regs;
	404
	405	serialnr->low = fuse->tester0;
	406	serialnr->high = fuse->tester1;
	407	}
	408	#endif
	409
c5752f73 AA	410	void set_wdog_reset(struct wdog_regs *wdog)
	411	{
	412	u32 reg = readw(&wdog->wcr);
	413	/*
	414	* Output WDOG_B signal to reset external pmic or POR_B decided by
	415	* the board desgin. Without external reset, the peripherals/DDR/
	416	* PMIC are not reset, that may cause system working abnormal.
	417	*/
	418	reg = readw(&wdog->wcr);
	419	reg \|= 1 << 3;
	420	/*
	421	* WDZST bit is write-once only bit. Align this bit in kernel,
	422	* otherwise kernel code will have no chance to set this bit.
	423	*/
	424	reg \|= 1 << 0;
	425	writew(reg, &wdog->wcr);
	426	}
	427
c5752f73 AA	428	void s_init(void)
c5752f73 AA	429	{
c5752f73 AA	430	/* clock configuration. */
	431	clock_init();
	432
	433	return;
	434	}
9f8fa184	435
c72372d3 MV	436	#ifndef CONFIG_SPL_BUILD
	437	const struct boot_mode soc_boot_modes[] = {
	438	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
5ec83561 MV	439	{"primary", MAKE_CFGVAL_PRIMARY_BOOT},
5ec83561 MV	440	{"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
c72372d3 MV	441	{NULL, 0},
c72372d3 MV	442	};
4b44bea7 MV	443
	444	int boot_mode_getprisec(void)
	445	{
	446	struct src psrc = (struct src )SRC_BASE_ADDR;
	447
	448	return !!(readl(&psrc->gpr10) & IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT);
	449	}
c72372d3 MV	450	#endif
c72372d3 MV	451
9f8fa184 PF	452	void reset_misc(void)
9f8fa184 PF	453	{
bab289cb	454	#ifndef CONFIG_SPL_BUILD
b86986c7	455	#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
9f8fa184 PF	456	lcdif_power_down();
9f8fa184 PF	457	#endif
bab289cb	458	#endif
9f8fa184	459	}