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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c67bee14 SB |
2 | /* |
3 | * (C) Copyright 2000-2003 | |
4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
5 | * | |
6 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
c67bee14 SB |
8 | */ |
9 | ||
d678a59d | 10 | #include <common.h> |
d96c2604 | 11 | #include <clock_legacy.h> |
c67bee14 | 12 | #include <asm/arch/imx-regs.h> |
e4d34492 | 13 | #include <asm/arch/clock.h> |
401d1c4f | 14 | #include <asm/global_data.h> |
c67bee14 | 15 | |
e37ac717 | 16 | #ifdef CONFIG_FSL_ESDHC_IMX |
29565326 JR |
17 | DECLARE_GLOBAL_DATA_PTR; |
18 | #endif | |
19 | ||
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20 | int get_clocks(void) |
21 | { | |
e37ac717 | 22 | #ifdef CONFIG_FSL_ESDHC_IMX |
5c23712d | 23 | #ifdef CONFIG_FSL_USDHC |
6cc04547 | 24 | #if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR |
e9adeca3 | 25 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
6cc04547 | 26 | #elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR |
e9adeca3 | 27 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
6cc04547 | 28 | #elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR |
e9adeca3 | 29 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
32384656 | 30 | #else |
e9adeca3 | 31 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
32384656 BT |
32 | #endif |
33 | #else | |
6cc04547 | 34 | #if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR |
e9adeca3 | 35 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
6cc04547 | 36 | #elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR |
e9adeca3 | 37 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
6cc04547 | 38 | #elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR |
e9adeca3 | 39 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
5c23712d | 40 | #else |
e9adeca3 | 41 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
32384656 | 42 | #endif |
5c23712d | 43 | #endif |
c67bee14 SB |
44 | #endif |
45 | return 0; | |
46 | } |