[people/ms/u-boot.git] / arch / arm / mach-kirkwood / include / mach / config.h

/*
 * (C) Copyright 2011
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * This file should be included in board config header file.
 *
 * It supports common definitions for Kirkwood platform
 */

#ifndef _KW_CONFIG_H
#define _KW_CONFIG_H

#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
#include <asm/arch/kw88f6192.h>
#else
#error "SOC Name not defined"
#endif /* CONFIG_KW88F6281 */

#include <asm/arch/soc.h>
#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */

/*
 * By default kwbimage.cfg from board specific folder is used
 * If for some board, different configuration file need to be used,
 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
 */
#ifndef CONFIG_SYS_KWD_CONFIG
#define	CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */

/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
#define CONFIG_NR_DRAM_BANKS_MAX	2

#define CONFIG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
#define MV_SATA_BASE		KW_SATA_BASE
#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET

/*
 * NAND configuration
 */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL		1
#endif

/*
 * SPI Flash configuration
 */
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI			1
#define CONFIG_KIRKWOOD_SPI		1
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS		0
#endif
#ifndef CONFIG_ENV_SPI_CS
# define CONFIG_ENV_SPI_CS		0
#endif
#ifndef CONFIG_ENV_SPI_MAX_HZ
# define CONFIG_ENV_SPI_MAX_HZ		50000000
#endif
#endif

/*
 * Ethernet Driver configuration
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_MII		/* expose smi ove miiphy interface */
#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */

/*
 * USB/EHCI
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */

/*
 * IDE Support on SATA ports
 */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS		2
#define CONFIG_SYS_IDE_MAXDEVICE	2
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
#endif /* CONFIG_CMD_IDE */

/*
 * I2C related stuff
 */
#ifdef CONFIG_CMD_I2C
#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#endif
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000
#endif

/* Use common timer */
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(MVEBU_TIMER_BASE + 0x14)
#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_TCLK

#endif /* _KW_CONFIG_H */
Commit	Line	Data
cf946c6d LW	1	/*
	2	* (C) Copyright 2011
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Lei Wen <leiwen@marvell.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
cf946c6d LW	7	*/
	8
	9	/*
	10	* This file should be included in board config header file.
	11	*
	12	* It supports common definitions for Kirkwood platform
	13	*/
	14
	15	#ifndef _KW_CONFIG_H
	16	#define _KW_CONFIG_H
	17
	18	#if defined (CONFIG_KW88F6281)
	19	#include <asm/arch/kw88f6281.h>
	20	#elif defined (CONFIG_KW88F6192)
	21	#include <asm/arch/kw88f6192.h>
	22	#else
	23	#error "SOC Name not defined"
	24	#endif /* CONFIG_KW88F6281 */
	25
3dc23f78	26	#include <asm/arch/soc.h>
cf946c6d LW	27	#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
	28	#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
	29	#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
	30
	31	/*
	32	* By default kwbimage.cfg from board specific folder is used
	33	* If for some board, different configuration file need to be used,
	34	* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
	35	*/
	36	#ifndef CONFIG_SYS_KWD_CONFIG
4ab3fc5e	37	#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
cf946c6d LW	38	#endif /* CONFIG_SYS_KWD_CONFIG */
	39
	40	/* Kirkwood has 2k of Security SRAM, use it for SP */
	41	#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
	42	#define CONFIG_NR_DRAM_BANKS_MAX 2
	43
dd82242b	44	#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
cf946c6d LW	45	#define MV_UART_CONSOLE_BASE KW_UART0_BASE
	46	#define MV_SATA_BASE KW_SATA_BASE
	47	#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
	48	#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
	49
	50	/*
	51	* NAND configuration
	52	*/
	53	#ifdef CONFIG_CMD_NAND
	54	#define CONFIG_NAND_KIRKWOOD
	55	#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
	56	#define NAND_ALLOW_ERASE_ALL 1
	57	#endif
	58
	59	/*
	60	* SPI Flash configuration
	61	*/
	62	#ifdef CONFIG_CMD_SF
	63	#define CONFIG_HARD_SPI 1
	64	#define CONFIG_KIRKWOOD_SPI 1
dacc8c6f VL	65	#ifndef CONFIG_ENV_SPI_BUS
	66	# define CONFIG_ENV_SPI_BUS 0
	67	#endif
	68	#ifndef CONFIG_ENV_SPI_CS
	69	# define CONFIG_ENV_SPI_CS 0
	70	#endif
	71	#ifndef CONFIG_ENV_SPI_MAX_HZ
	72	# define CONFIG_ENV_SPI_MAX_HZ 50000000
	73	#endif
cf946c6d LW	74	#endif
	75
	76	/*
	77	* Ethernet Driver configuration
	78	*/
	79	#ifdef CONFIG_CMD_NET
cf946c6d	80	#define CONFIG_NETCONSOLE /* include NetConsole support */
cf946c6d LW	81	#define CONFIG_MII /* expose smi ove miiphy interface */
	82	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
	83	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
	84	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
	85	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
	86	#endif /* CONFIG_CMD_NET */
	87
	88	/*
	89	* USB/EHCI
	90	*/
	91	#ifdef CONFIG_CMD_USB
cf946c6d LW	92	#define CONFIG_EHCI_IS_TDI
	93	#endif /* CONFIG_CMD_USB */
	94
	95	/*
	96	* IDE Support on SATA ports
	97	*/
	98	#ifdef CONFIG_CMD_IDE
	99	#define __io
cf946c6d LW	100	#define CONFIG_MVSATA_IDE
	101	#define CONFIG_IDE_PREINIT
	102	#define CONFIG_MVSATA_IDE_USE_PORT1
	103	/* Needs byte-swapping for ATA data register */
	104	#define CONFIG_IDE_SWAP_IO
	105	/* Data, registers and alternate blocks are at the same offset */
	106	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
	107	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
	108	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
	109	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	110	#define CONFIG_SYS_ATA_STRIDE 4
	111	/* Controller supports 48-bits LBA addressing */
	112	#define CONFIG_LBA48
	113	/* CONFIG_CMD_IDE requires some #defines for ATA registers */
	114	#define CONFIG_SYS_IDE_MAXBUS 2
	115	#define CONFIG_SYS_IDE_MAXDEVICE 2
	116	/* ATA registers base is at SATA controller base */
	117	#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
	118	#endif /* CONFIG_CMD_IDE */
	119
	120	/*
	121	* I2C related stuff
	122	*/
	123	#ifdef CONFIG_CMD_I2C
ea818dbb	124	#ifndef CONFIG_SYS_I2C_SOFT
0db2bbdc HG	125	#define CONFIG_SYS_I2C
0db2bbdc HG	126	#define CONFIG_SYS_I2C_MVTWSI
b31a82e9	127	#endif
cf946c6d LW	128	#define CONFIG_SYS_I2C_SLAVE 0x0
	129	#define CONFIG_SYS_I2C_SPEED 100000
	130	#endif
	131
2fbc18fe SR	132	/* Use common timer */
	133	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	134	#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
	135	#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
	136
cf946c6d	137	#endif /* _KW_CONFIG_H */