]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
52f69f81 | 2 | /* |
576007ae | 3 | * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com> |
52f69f81 VZ |
4 | */ |
5 | ||
d678a59d | 6 | #include <common.h> |
1eb69ae4 | 7 | #include <cpu_func.h> |
691d719d | 8 | #include <init.h> |
90526e9f | 9 | #include <net.h> |
ac2916a2 | 10 | #include <netdev.h> |
52f69f81 VZ |
11 | #include <asm/arch/cpu.h> |
12 | #include <asm/arch/clk.h> | |
13 | #include <asm/arch/wdt.h> | |
412ae53a | 14 | #include <asm/arch/sys_proto.h> |
52f69f81 VZ |
15 | #include <asm/io.h> |
16 | ||
17 | static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; | |
18 | static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; | |
19 | ||
35b65dd8 | 20 | void reset_cpu(void) |
52f69f81 VZ |
21 | { |
22 | /* Enable watchdog clock */ | |
23 | setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); | |
24 | ||
3394f398 HS |
25 | /* Reset pulse length is 13005 peripheral clock frames */ |
26 | writel(13000, &wdt->pulse); | |
52f69f81 | 27 | |
3394f398 HS |
28 | /* Force WDOG_RESET2 and RESOUT_N signal active */ |
29 | writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, | |
30 | &wdt->mctrl); | |
52f69f81 VZ |
31 | |
32 | while (1) | |
33 | /* NOP */; | |
34 | } | |
35 | ||
36 | #if defined(CONFIG_ARCH_CPU_INIT) | |
37 | int arch_cpu_init(void) | |
38 | { | |
39 | /* | |
a187559e | 40 | * It might be necessary to flush data cache, if U-Boot is loaded |
52f69f81 VZ |
41 | * from kickstart bootloader, e.g. from S1L loader |
42 | */ | |
43 | flush_dcache_all(); | |
44 | ||
45 | return 0; | |
46 | } | |
47 | #else | |
48 | #error "You have to select CONFIG_ARCH_CPU_INIT" | |
49 | #endif | |
50 | ||
51 | #if defined(CONFIG_DISPLAY_CPUINFO) | |
52 | int print_cpuinfo(void) | |
53 | { | |
54 | printf("CPU: NXP LPC32XX\n"); | |
55 | printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000); | |
56 | printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000); | |
57 | printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000); | |
58 | ||
59 | return 0; | |
60 | } | |
61 | #endif |