[thirdparty/u-boot.git] / arch / arm / mach-lpc32xx / devices.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
 */

#include <common.h>
#include <dm.h>
#include <ns16550.h>

#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/arch/mux.h>
#include <asm/io.h>

static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;

void lpc32xx_uart_init(unsigned int uart_id)
{
	if (uart_id < 1 || uart_id > 7)
		return;

	/* Disable loopback mode, if it is set by S1L bootloader */
	clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));

	if (uart_id < 3 || uart_id > 6)
		return;

	/* Enable UART system clock */
	setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));

	/* Set UART into autoclock mode */
	clrsetbits_le32(&ctrl->clkmode,
			UART_CLKMODE_MASK(uart_id),
			UART_CLKMODE_AUTO(uart_id));

	/* Bypass pre-divider of UART clock */
	writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
	       &clk->u3clk + (uart_id - 3));
}

#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_plat lpc32xx_uart[] = {
	{ .base = UART3_BASE, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	{ .base = UART4_BASE, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	{ .base = UART5_BASE, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
	{ .base = UART6_BASE, .reg_shift = 2,
	  .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
};

U_BOOT_DRVINFOS(lpc32xx_uarts) = {
	{ "ns16550_serial", &lpc32xx_uart[0], },
	{ "ns16550_serial", &lpc32xx_uart[1], },
	{ "ns16550_serial", &lpc32xx_uart[2], },
	{ "ns16550_serial", &lpc32xx_uart[3], },
};
#endif

void lpc32xx_dma_init(void)
{
	/* Enable DMA interface */
	writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
}

void lpc32xx_mac_init(void)
{
	/* Enable MAC interface */
	writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
#if defined(CONFIG_RMII)
		| CLK_MAC_RMII,
#else
		| CLK_MAC_MII,
#endif
		&clk->macclk_ctrl);
}

void lpc32xx_mlc_nand_init(void)
{
	/* Enable NAND interface */
	writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
}

void lpc32xx_slc_nand_init(void)
{
	/* Enable SLC NAND interface */
	writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
}

void lpc32xx_usb_init(void)
{
	/* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
	clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
}

void lpc32xx_i2c_init(unsigned int devnum)
{
	/* Enable I2C interface */
	uint32_t ctrl = readl(&clk->i2cclk_ctrl);
	if (devnum == 1)
		ctrl |= CLK_I2C1_ENABLE;
	if (devnum == 2)
		ctrl |= CLK_I2C2_ENABLE;
	writel(ctrl, &clk->i2cclk_ctrl);
}

U_BOOT_DRVINFO(lpc32xx_gpios) = {
	.name = "gpio_lpc32xx"
};

/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */

#define P_MUX_SET_SSP0 0x1600

void lpc32xx_ssp_init(void)
{
	/* Enable SSP0 interface */
	writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
	/* Mux SSP0 pins */
	writel(P_MUX_SET_SSP0, &mux->p_mux_set);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
52f69f81 VZ	2	/*
52f69f81 VZ	3	* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
52f69f81 VZ	4	*/
52f69f81 VZ	5
d678a59d	6	#include <common.h>
d25ba89e VZ	7	#include <dm.h>
d25ba89e VZ	8	#include <ns16550.h>
d25ba89e	9
52f69f81 VZ	10	#include <asm/arch/clk.h>
52f69f81 VZ	11	#include <asm/arch/uart.h>
981219ee	12	#include <asm/arch/mux.h>
52f69f81 VZ	13	#include <asm/io.h>
	14
	15	static struct clk_pm_regs clk = (struct clk_pm_regs )CLK_PM_BASE;
	16	static struct uart_ctrl_regs ctrl = (struct uart_ctrl_regs )UART_CTRL_BASE;
981219ee	17	static struct mux_regs mux = (struct mux_regs )MUX_BASE;
52f69f81 VZ	18
	19	void lpc32xx_uart_init(unsigned int uart_id)
	20	{
	21	if (uart_id < 1 \|\| uart_id > 7)
	22	return;
	23
	24	/* Disable loopback mode, if it is set by S1L bootloader */
bd4dbf9e	25	clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
52f69f81 VZ	26
	27	if (uart_id < 3 \|\| uart_id > 6)
	28	return;
	29
	30	/* Enable UART system clock */
	31	setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
	32
	33	/* Set UART into autoclock mode */
	34	clrsetbits_le32(&ctrl->clkmode,
	35	UART_CLKMODE_MASK(uart_id),
	36	UART_CLKMODE_AUTO(uart_id));
	37
	38	/* Bypass pre-divider of UART clock */
	39	writel(CLK_UART_X_DIV(1) \| CLK_UART_Y_DIV(1),
	40	&clk->u3clk + (uart_id - 3));
	41	}
ac2916a2	42
1222305b	43	#if !CONFIG_IS_ENABLED(OF_CONTROL)
8a8d24bd	44	static const struct ns16550_plat lpc32xx_uart[] = {
17fa0326	45	{ .base = UART3_BASE, .reg_shift = 2,
91092132	46	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
17fa0326	47	{ .base = UART4_BASE, .reg_shift = 2,
91092132	48	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
17fa0326	49	{ .base = UART5_BASE, .reg_shift = 2,
91092132	50	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
17fa0326	51	{ .base = UART6_BASE, .reg_shift = 2,
91092132	52	.clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
d25ba89e VZ	53	};
d25ba89e VZ	54
20e442ab	55	U_BOOT_DRVINFOS(lpc32xx_uarts) = {
d25ba89e VZ	56	{ "ns16550_serial", &lpc32xx_uart[0], },
	57	{ "ns16550_serial", &lpc32xx_uart[1], },
	58	{ "ns16550_serial", &lpc32xx_uart[2], },
	59	{ "ns16550_serial", &lpc32xx_uart[3], },
d25ba89e VZ	60	};
	61	#endif
	62
980db8ca SL	63	void lpc32xx_dma_init(void)
	64	{
	65	/* Enable DMA interface */
bab8d1e2	66	writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
980db8ca SL	67	}
980db8ca SL	68
ac2916a2 AA	69	void lpc32xx_mac_init(void)
	70	{
	71	/* Enable MAC interface */
	72	writel(CLK_MAC_REG \| CLK_MAC_SLAVE \| CLK_MAC_MASTER
1a791892 VZ	73	#if defined(CONFIG_RMII)
	74	\| CLK_MAC_RMII,
	75	#else
	76	\| CLK_MAC_MII,
	77	#endif
	78	&clk->macclk_ctrl);
ac2916a2	79	}
c8381bf4 AA	80
	81	void lpc32xx_mlc_nand_init(void)
	82	{
	83	/* Enable NAND interface */
	84	writel(CLK_NAND_MLC \| CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
	85	}
5e862b95	86
dcfd37e5 VZ	87	void lpc32xx_slc_nand_init(void)
	88	{
	89	/* Enable SLC NAND interface */
	90	writel(CLK_NAND_SLC \| CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
	91	}
	92
adf8d58d SL	93	void lpc32xx_usb_init(void)
	94	{
	95	/* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
	96	clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
	97	}
	98
5e862b95 AA	99	void lpc32xx_i2c_init(unsigned int devnum)
	100	{
	101	/* Enable I2C interface */
	102	uint32_t ctrl = readl(&clk->i2cclk_ctrl);
	103	if (devnum == 1)
	104	ctrl \|= CLK_I2C1_ENABLE;
	105	if (devnum == 2)
	106	ctrl \|= CLK_I2C2_ENABLE;
	107	writel(ctrl, &clk->i2cclk_ctrl);
	108	}
606f7047	109
20e442ab	110	U_BOOT_DRVINFO(lpc32xx_gpios) = {
606f7047 AA	111	.name = "gpio_lpc32xx"
606f7047 AA	112	};
981219ee AA	113
	114	/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
	115
	116	#define P_MUX_SET_SSP0 0x1600
	117
	118	void lpc32xx_ssp_init(void)
	119	{
	120	/* Enable SSP0 interface */
	121	writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
	122	/* Mux SSP0 pins */
	123	writel(P_MUX_SET_SSP0, &mux->p_mux_set);
	124	}