[thirdparty/u-boot.git] / arch / arm / mach-mediatek / mt8512 / init.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Configuration for MediaTek MT8512 SoC
 *
 * Copyright (C) 2019 MediaTek Inc.
 * Author: Mingming Lee <mingming.lee@mediatek.com>
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <init.h>
#include <log.h>
#include <ram.h>
#include <wdt.h>
#include <asm/arch/misc.h>
#include <asm/armv8/mmu.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/sections.h>
#include <dm/uclass.h>
#include <dt-bindings/clock/mt8512-clk.h>
#include <linux/sizes.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	return fdtdec_setup_mem_size_base();
}

phys_size_t  get_effective_memsize(void)
{
	/* limit stack below tee reserve memory */
	return gd->ram_size - 6 * SZ_1M;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = gd->ram_base;
	gd->bd->bi_dram[0].size = get_effective_memsize();

	return 0;
}

void reset_cpu(void)
{
	struct udevice *watchdog_dev = NULL;

	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
		if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
			psci_system_reset();

	wdt_expire_now(watchdog_dev, 0);
}

int print_cpuinfo(void)
{
	debug("CPU:   MediaTek MT8512\n");
	return 0;
}

static struct mm_region mt8512_mem_map[] = {
	{
		/* DDR */
		.virt = 0x40000000UL,
		.phys = 0x40000000UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
	}, {
		.virt = 0x00000000UL,
		.phys = 0x00000000UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		0,
	}
};

struct mm_region *mem_map = mt8512_mem_map;
Commit	Line	Data
953bb4c3	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Configuration for MediaTek MT8512 SoC
	4	*
	5	* Copyright (C) 2019 MediaTek Inc.
	6	* Author: Mingming Lee <mingming.lee@mediatek.com>
	7	*/
	8
	9	#include <clk.h>
d678a59d	10	#include <common.h>
953bb4c3	11	#include <dm.h>
953bb4c3	12	#include <fdtdec.h>
691d719d	13	#include <init.h>
f7ae49fc	14	#include <log.h>
953bb4c3	15	#include <ram.h>
	16	#include <wdt.h>
	17	#include <asm/arch/misc.h>
	18	#include <asm/armv8/mmu.h>
90526e9f	19	#include <asm/cache.h>
401d1c4f	20	#include <asm/global_data.h>
953bb4c3	21	#include <asm/sections.h>
	22	#include <dm/uclass.h>
	23	#include <dt-bindings/clock/mt8512-clk.h>
15713fc8	24	#include <linux/sizes.h>
953bb4c3	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	int dram_init(void)
	29	{
	30	return fdtdec_setup_mem_size_base();
	31	}
	32
	33	phys_size_t get_effective_memsize(void)
	34	{
	35	/* limit stack below tee reserve memory */
	36	return gd->ram_size - 6 * SZ_1M;
	37	}
	38
	39	int dram_init_banksize(void)
	40	{
	41	gd->bd->bi_dram[0].start = gd->ram_base;
	42	gd->bd->bi_dram[0].size = get_effective_memsize();
	43
	44	return 0;
	45	}
	46
35b65dd8	47	void reset_cpu(void)
953bb4c3	48	{
	49	struct udevice *watchdog_dev = NULL;
	50
	51	if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
	52	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
	53	psci_system_reset();
	54
	55	wdt_expire_now(watchdog_dev, 0);
	56	}
	57
	58	int print_cpuinfo(void)
	59	{
	60	debug("CPU: MediaTek MT8512\n");
	61	return 0;
	62	}
	63
	64	static struct mm_region mt8512_mem_map[] = {
	65	{
	66	/* DDR */
	67	.virt = 0x40000000UL,
	68	.phys = 0x40000000UL,
	69	.size = 0x40000000UL,
	70	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \| PTE_BLOCK_OUTER_SHARE,
	71	}, {
	72	.virt = 0x00000000UL,
	73	.phys = 0x00000000UL,
	74	.size = 0x40000000UL,
	75	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	76	PTE_BLOCK_NON_SHARE \|
	77	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	78	}, {
	79	0,
	80	}
	81	};
	82
	83	struct mm_region *mem_map = mt8512_mem_map;