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def2fc05 FP |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2018 MediaTek Inc. | |
4 | * Copyright (C) 2019 BayLibre, SAS | |
5 | * Author: Fabien Parent <fparent@baylibre.com> | |
6 | */ | |
7 | ||
8 | #include <clk.h> | |
d678a59d | 9 | #include <common.h> |
9a3b4ceb | 10 | #include <cpu_func.h> |
def2fc05 FP |
11 | #include <dm.h> |
12 | #include <fdtdec.h> | |
691d719d | 13 | #include <init.h> |
def2fc05 FP |
14 | #include <ram.h> |
15 | #include <asm/arch/misc.h> | |
16 | #include <asm/armv8/mmu.h> | |
90526e9f | 17 | #include <asm/cache.h> |
401d1c4f | 18 | #include <asm/global_data.h> |
def2fc05 FP |
19 | #include <asm/sections.h> |
20 | #include <dm/uclass.h> | |
def2fc05 FP |
21 | #include <dt-bindings/clock/mt8516-clk.h> |
22 | ||
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
def2fc05 FP |
25 | int dram_init(void) |
26 | { | |
27 | int ret; | |
28 | ||
29 | ret = fdtdec_setup_memory_banksize(); | |
30 | if (ret) | |
31 | return ret; | |
32 | ||
33 | return fdtdec_setup_mem_size_base(); | |
34 | } | |
35 | ||
36 | int dram_init_banksize(void) | |
37 | { | |
38 | gd->bd->bi_dram[0].start = gd->ram_base; | |
39 | gd->bd->bi_dram[0].size = gd->ram_size; | |
40 | ||
41 | return 0; | |
42 | } | |
43 | ||
44 | int mtk_pll_early_init(void) | |
45 | { | |
46 | unsigned long pll_rates[] = { | |
47 | [CLK_APMIXED_ARMPLL] = 1300000000, | |
48 | [CLK_APMIXED_MAINPLL] = 1501000000, | |
49 | [CLK_APMIXED_UNIVPLL] = 1248000000, | |
50 | [CLK_APMIXED_MMPLL] = 380000000, | |
51 | }; | |
52 | struct udevice *dev; | |
53 | int ret, i; | |
54 | ||
55 | ret = uclass_get_device_by_driver(UCLASS_CLK, | |
65e25bea | 56 | DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); |
def2fc05 FP |
57 | if (ret) |
58 | return ret; | |
59 | ||
60 | /* configure default rate then enable apmixedsys */ | |
61 | for (i = 0; i < ARRAY_SIZE(pll_rates); i++) { | |
62 | struct clk clk = { .id = i, .dev = dev }; | |
63 | ||
64 | ret = clk_set_rate(&clk, pll_rates[i]); | |
65 | if (ret) | |
66 | return ret; | |
67 | ||
68 | ret = clk_enable(&clk); | |
69 | if (ret) | |
70 | return ret; | |
71 | } | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | int mtk_soc_early_init(void) | |
77 | { | |
78 | int ret; | |
79 | ||
80 | /* initialize early clocks */ | |
81 | ret = mtk_pll_early_init(); | |
82 | if (ret) | |
83 | return ret; | |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
35b65dd8 | 88 | void reset_cpu(void) |
def2fc05 | 89 | { |
47f30aaa | 90 | psci_system_reset(); |
def2fc05 FP |
91 | } |
92 | ||
93 | int print_cpuinfo(void) | |
94 | { | |
95 | printf("CPU: MediaTek MT8516\n"); | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static struct mm_region mt8516_mem_map[] = { | |
100 | { | |
101 | /* DDR */ | |
102 | .virt = 0x40000000UL, | |
103 | .phys = 0x40000000UL, | |
104 | .size = 0x20000000UL, | |
105 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, | |
106 | }, { | |
107 | .virt = 0x00000000UL, | |
108 | .phys = 0x00000000UL, | |
109 | .size = 0x20000000UL, | |
110 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
111 | PTE_BLOCK_NON_SHARE | | |
112 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
113 | }, { | |
114 | 0, | |
115 | } | |
116 | }; | |
117 | struct mm_region *mem_map = mt8516_mem_map; |