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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
21b29fc6 SR |
2 | /* |
3 | * Copyright (C) 2016 Stefan Roese <sr@denx.de> | |
21b29fc6 SR |
4 | */ |
5 | ||
d678a59d | 6 | #include <common.h> |
21b29fc6 SR |
7 | #include <dm.h> |
8 | #include <fdtdec.h> | |
67c4e9f8 | 9 | #include <init.h> |
90526e9f | 10 | #include <asm/cache.h> |
401d1c4f | 11 | #include <asm/global_data.h> |
25a5818f | 12 | #include <asm/ptrace.h> |
b08c8c48 | 13 | #include <linux/libfdt.h> |
2b4d9647 | 14 | #include <linux/sizes.h> |
f4f194e8 | 15 | #include <pci.h> |
21b29fc6 SR |
16 | #include <asm/io.h> |
17 | #include <asm/system.h> | |
18 | #include <asm/arch/cpu.h> | |
19 | #include <asm/arch/soc.h> | |
20 | #include <asm/armv8/mmu.h> | |
21 | ||
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
059f75d5 SR |
24 | /* |
25 | * Not all memory is mapped in the MMU. So we need to restrict the | |
26 | * memory size so that U-Boot does not try to access it. Also, the | |
27 | * internal registers are located at 0xf000.0000 - 0xffff.ffff. | |
28 | * Currently only 2GiB are mapped for system memory. This is what | |
29 | * we pass to the U-Boot subsystem here. | |
30 | */ | |
8fd3cf29 | 31 | #define USABLE_RAM_SIZE 0x80000000ULL |
059f75d5 | 32 | |
d768dd88 | 33 | phys_addr_t board_get_usable_ram_top(phys_size_t total_size) |
059f75d5 | 34 | { |
aa6e94de | 35 | unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); |
059f75d5 | 36 | |
8fd3cf29 | 37 | return (gd->ram_top > top) ? top : gd->ram_top; |
059f75d5 SR |
38 | } |
39 | ||
21b29fc6 SR |
40 | /* |
41 | * On ARMv8, MBus is not configured in U-Boot. To enable compilation | |
42 | * of the already implemented drivers, lets add a dummy version of | |
43 | * this function so that linking does not fail. | |
44 | */ | |
45 | const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) | |
46 | { | |
47 | return NULL; | |
48 | } | |
49 | ||
3b281aca | 50 | __weak int dram_init_banksize(void) |
21b29fc6 | 51 | { |
611e9af0 | 52 | if (IS_ENABLED(CONFIG_ARMADA_8K)) |
f075b425 | 53 | return a8k_dram_init_banksize(); |
c1c5538e | 54 | else if (IS_ENABLED(CONFIG_ARMADA_3700)) |
a129f64f | 55 | return a3700_dram_init_banksize(); |
51864cdc | 56 | else if (IS_ENABLED(CONFIG_ALLEYCAT_5)) |
7d7bb99e | 57 | return alleycat5_dram_init_banksize(); |
2b4d9647 | 58 | else |
f075b425 | 59 | return fdtdec_setup_memory_banksize(); |
21b29fc6 SR |
60 | } |
61 | ||
3b281aca | 62 | __weak int dram_init(void) |
21b29fc6 | 63 | { |
611e9af0 | 64 | if (IS_ENABLED(CONFIG_ARMADA_8K)) { |
2b4d9647 BS |
65 | gd->ram_size = a8k_dram_scan_ap_sz(); |
66 | if (gd->ram_size != 0) | |
67 | return 0; | |
68 | } | |
69 | ||
c1c5538e | 70 | if (IS_ENABLED(CONFIG_ARMADA_3700)) |
a129f64f MB |
71 | return a3700_dram_init(); |
72 | ||
51864cdc | 73 | if (IS_ENABLED(CONFIG_ALLEYCAT_5)) |
7d7bb99e CP |
74 | return alleycat5_dram_init(); |
75 | ||
12308b12 | 76 | if (fdtdec_setup_mem_size_base() != 0) |
21b29fc6 SR |
77 | return -EINVAL; |
78 | ||
76b00aca | 79 | return 0; |
21b29fc6 SR |
80 | } |
81 | ||
82 | int arch_cpu_init(void) | |
83 | { | |
84 | /* Nothing to do (yet) */ | |
85 | return 0; | |
86 | } | |
87 | ||
88 | int arch_early_init_r(void) | |
89 | { | |
90 | struct udevice *dev; | |
91 | int ret; | |
d7dd358f SR |
92 | int i; |
93 | ||
94 | /* | |
95 | * Loop over all MISC uclass drivers to call the comphy code | |
96 | * and init all CP110 devices enabled in the DT | |
97 | */ | |
98 | i = 0; | |
99 | while (1) { | |
100 | /* Call the comphy code via the MISC uclass driver */ | |
101 | ret = uclass_get_device(UCLASS_MISC, i++, &dev); | |
102 | ||
103 | /* We're done, once no further CP110 device is found */ | |
104 | if (ret) | |
105 | break; | |
21b29fc6 SR |
106 | } |
107 | ||
108 | /* Cause the SATA device to do its early init */ | |
109 | uclass_first_device(UCLASS_AHCI, &dev); | |
110 | ||
f4f194e8 | 111 | /* Trigger PCIe devices detection */ |
ebacc78e SG |
112 | if (IS_ENABLED(CONFIG_PCI)) |
113 | pci_init(); | |
f4f194e8 | 114 | |
21b29fc6 SR |
115 | return 0; |
116 | } |