[thirdparty/u-boot.git] / arch / arm / mach-mvebu / armada3700 / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
 * Copyright (C) 2020 Marek Behún <kabel@kernel.org>
 */

#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
#include <sort.h>

/* Armada 3700 */
#define MVEBU_GPIO_NB_REG_BASE		(MVEBU_REGISTER(0x13800))

#define MVEBU_TEST_PIN_LATCH_N		(MVEBU_GPIO_NB_REG_BASE + 0x8)
#define MVEBU_XTAL_MODE_MASK		BIT(9)
#define MVEBU_XTAL_MODE_OFFS		9
#define MVEBU_XTAL_CLOCK_25MHZ		0x0
#define MVEBU_XTAL_CLOCK_40MHZ		0x1

#define MVEBU_NB_WARM_RST_REG		(MVEBU_GPIO_NB_REG_BASE + 0x40)
#define MVEBU_NB_WARM_RST_MAGIC_NUM	0x1d1e

/* Armada 3700 CPU Address Decoder registers */
#define MVEBU_CPU_DEC_WIN_REG_BASE	(size_t)(MVEBU_REGISTER(0xcf00))
#define MVEBU_CPU_DEC_WIN_CTRL(w) \
	(MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
#define MVEBU_CPU_DEC_WIN_CTRL_EN	BIT(0)
#define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK	0xf
#define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS	4
#define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM	0
#define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE	2
#define MVEBU_CPU_DEC_WIN_SIZE(w)	(MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
#define MVEBU_CPU_DEC_WIN_BASE(w)	(MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
#define MVEBU_CPU_DEC_WIN_REMAP(w)	(MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
#define MVEBU_CPU_DEC_WIN_GRANULARITY	16
#define MVEBU_CPU_DEC_WINS		5
#define MVEBU_CPU_DEC_CCI_BASE		(MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
#define MVEBU_CPU_DEC_ROM_BASE		(MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4)

#define MAX_MEM_MAP_REGIONS		(MVEBU_CPU_DEC_WINS + 4)

#define A3700_PTE_BLOCK_NORMAL \
	(PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
#define A3700_PTE_BLOCK_DEVICE \
	(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)

DECLARE_GLOBAL_DATA_PTR;

static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
	{
		/*
		 * SRAM, MMIO regions
		 * Don't remove this, build_mem_map needs it.
		 */
		.phys = SOC_REGS_PHY_BASE,
		.virt = SOC_REGS_PHY_BASE,
		.size = 0x02000000UL,	/* 32MiB internal registers */
		.attrs = A3700_PTE_BLOCK_DEVICE
	},
};

struct mm_region *mem_map = mvebu_mem_map;

static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
{
	u32 reg;

	reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
	if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
		return -1;

	if (tgt) {
		reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
		reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
		*tgt = reg;
	}

	if (base) {
		reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
		*base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
	}

	if (size) {
		/*
		 * Window size is encoded as the number of 1s from LSB to MSB,
		 * followed by 0s. The number of 1s specifies the size in 64 KiB
		 * granularity.
		 */
		reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
		*size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
	}

	return 0;
}

/*
 * Builds mem_map according to CPU Address Decoder settings, which were set by
 * the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
 */
static void build_mem_map(void)
{
	int win, region;
	u32 reg;

	region = 1;

	/* CCI-400 */
	reg = readl(MVEBU_CPU_DEC_CCI_BASE);
	mvebu_mem_map[region].phys = reg << 20;
	mvebu_mem_map[region].virt = reg << 20;
	mvebu_mem_map[region].size = SZ_64K;
	mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE;
	++region;

	/* AP BootROM */
	reg = readl(MVEBU_CPU_DEC_ROM_BASE);
	mvebu_mem_map[region].phys = reg << 20;
	mvebu_mem_map[region].virt = reg << 20;
	mvebu_mem_map[region].size = SZ_1M;
	mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL;
	++region;

	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
		u32 base, tgt, size;
		u64 attrs;

		/* skip disabled windows */
		if (get_cpu_dec_win(win, &tgt, &base, &size))
			continue;

		if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
			attrs = A3700_PTE_BLOCK_NORMAL;
		else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
			attrs = A3700_PTE_BLOCK_DEVICE;
		else
			/* skip windows with other targets */
			continue;

		mvebu_mem_map[region].phys = base;
		mvebu_mem_map[region].virt = base;
		mvebu_mem_map[region].size = size;
		mvebu_mem_map[region].attrs = attrs;
		++region;
	}

	/* add list terminator */
	mvebu_mem_map[region].size = 0;
	mvebu_mem_map[region].attrs = 0;
}

void enable_caches(void)
{
	icache_enable();
	dcache_enable();
}

int a3700_dram_init(void)
{
	int win;

	build_mem_map();

	gd->ram_size = 0;
	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
		u32 base, tgt, size;

		/* skip disabled windows */
		if (get_cpu_dec_win(win, &tgt, &base, &size))
			continue;

		/* skip non-DRAM windows */
		if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
			continue;

		/*
		 * It is possible that one image was built for boards with
		 * different RAM sizes, for example 512 MiB and 1 GiB.
		 * We therefore try to determine the actual RAM size in the
		 * window with get_ram_size.
		 */
		gd->ram_size += get_ram_size((void *)(size_t)base, size);
	}

	return 0;
}

struct a3700_dram_window {
	size_t base, size;
};

static int dram_win_cmp(const void *a, const void *b)
{
	size_t ab, bb;

	ab = ((const struct a3700_dram_window *)a)->base;
	bb = ((const struct a3700_dram_window *)b)->base;

	if (ab < bb)
		return -1;
	else if (ab > bb)
		return 1;
	else
		return 0;
}

int a3700_dram_init_banksize(void)
{
	struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
	int bank, win, ndram_wins;
	u32 last_end;
	size_t size;

	ndram_wins = 0;
	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
		u32 base, tgt, size;

		/* skip disabled windows */
		if (get_cpu_dec_win(win, &tgt, &base, &size))
			continue;

		/* skip non-DRAM windows */
		if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
			continue;

		dram_wins[win].base = base;
		dram_wins[win].size = size;
		++ndram_wins;
	}

	qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);

	bank = 0;
	last_end = -1;

	for (win = 0; win < ndram_wins; ++win) {
		/* again determining actual RAM size as in a3700_dram_init */
		size = get_ram_size((void *)dram_wins[win].base,
				    dram_wins[win].size);

		/*
		 * Check if previous window ends as the current starts. If yes,
		 * merge these windows into one "bank". This is possible by this
		 * simple check thanks to mem_map regions being qsorted in
		 * build_mem_map.
		 */
		if (last_end == dram_wins[win].base) {
			gd->bd->bi_dram[bank - 1].size += size;
			last_end += size;
		} else {
			if (bank == CONFIG_NR_DRAM_BANKS) {
				printf("Need more CONFIG_NR_DRAM_BANKS\n");
				return -ENOBUFS;
			}

			gd->bd->bi_dram[bank].start = dram_wins[win].base;
			gd->bd->bi_dram[bank].size = size;
			last_end = dram_wins[win].base + size;
			++bank;
		}
	}

	/*
	 * If there is more place for DRAM BANKS definitions than needed, fill
	 * the rest with zeros.
	 */
	for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
		gd->bd->bi_dram[bank].start = 0;
		gd->bd->bi_dram[bank].size = 0;
	}

	return 0;
}

static u32 find_pcie_window_base(void)
{
	int win;

	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
		u32 base, tgt;

		/* skip disabled windows */
		if (get_cpu_dec_win(win, &tgt, &base, NULL))
			continue;

		if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
			return base;
	}

	return -1;
}

static int fdt_setprop_inplace_u32_partial(void *blob, int node,
					   const char *name,
					   u32 idx, u32 val)
{
	val = cpu_to_fdt32(val);

	return fdt_setprop_inplace_namelen_partial(blob, node, name,
						   strlen(name),
						   idx * sizeof(u32),
						   &val, sizeof(u32));
}

int a3700_fdt_fix_pcie_regions(void *blob)
{
	u32 base, lowest_cpu_addr, fix_offset;
	int pci_cells, cpu_cells, size_cells;
	const u32 *ranges;
	int node, pnode;
	int ret, i, len;

	base = find_pcie_window_base();
	if (base == -1)
		return -ENOENT;

	node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-3700-pcie");
	if (node < 0)
		return node;

	ranges = fdt_getprop(blob, node, "ranges", &len);
	if (!ranges || !len || len % sizeof(u32))
		return -EINVAL;

	/*
	 * The "ranges" property is an array of
	 *   { <PCI address> <CPU address> <size in PCI address space> }
	 * where number of PCI address cells and size cells is stored in the
	 * "#address-cells" and "#size-cells" properties of the same node
	 * containing the "ranges" property and number of CPU address cells
	 * is stored in the parent's "#address-cells" property.
	 *
	 * All 3 elements can span a diffent number of cells. Fetch them.
	 */
	pnode = fdt_parent_offset(blob, node);
	pci_cells = fdt_address_cells(blob, node);
	cpu_cells = fdt_address_cells(blob, pnode);
	size_cells = fdt_size_cells(blob, node);

	/* PCI addresses always use 3 cells */
	if (pci_cells != 3)
		return -EINVAL;

	/* CPU addresses on Armada 37xx always use 2 cells */
	if (cpu_cells != 2)
		return -EINVAL;

	for (i = 0; i < len / sizeof(u32);
	     i += pci_cells + cpu_cells + size_cells) {
		/*
		 * Parent CPU addresses on Armada 37xx are always 32-bit, so
		 * check that the high word is zero.
		 */
		if (fdt32_to_cpu(ranges[i + pci_cells]))
			return -EINVAL;

		if (i == 0 ||
		    fdt32_to_cpu(ranges[i + pci_cells + 1]) < lowest_cpu_addr)
			lowest_cpu_addr = fdt32_to_cpu(ranges[i + pci_cells + 1]);
	}

	/* Calculate fixup offset from the lowest (first) CPU address */
	fix_offset = base - lowest_cpu_addr;

	/* If fixup offset is zero there is nothing to fix */
	if (!fix_offset)
		return 0;

	/*
	 * Fix each CPU address and corresponding PCI address if PCI address
	 * is not already remapped (has the same value)
	 */
	for (i = 0; i < len / sizeof(u32);
	     i += pci_cells + cpu_cells + size_cells) {
		u32 cpu_addr;
		u64 pci_addr;
		int idx;

		/* Fix CPU address */
		idx = i + pci_cells + cpu_cells - 1;
		cpu_addr = fdt32_to_cpu(ranges[idx]);
		ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
						      cpu_addr + fix_offset);
		if (ret)
			return ret;

		/* Fix PCI address only if it isn't remapped (is same as CPU) */
		idx = i + pci_cells - 1;
		pci_addr = ((u64)fdt32_to_cpu(ranges[idx - 1]) << 32) |
			   fdt32_to_cpu(ranges[idx]);
		if (cpu_addr != pci_addr)
			continue;

		ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
						      cpu_addr + fix_offset);
		if (ret)
			return ret;
	}

	return 0;
}

void reset_cpu(void)
{
	/*
	 * Write magic number of 0x1d1e to North Bridge Warm Reset register
	 * to trigger warm reset
	 */
	writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
}

/*
 * get_ref_clk
 *
 * return: reference clock in MHz (25 or 40)
 */
u32 get_ref_clk(void)
{
	u32 regval;

	regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
		MVEBU_XTAL_MODE_OFFS;

	if (regval == MVEBU_XTAL_CLOCK_25MHZ)
		return 25;
	else
		return 40;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f61aefc1 SR	2	/*
f61aefc1 SR	3	* Copyright (C) 2016 Stefan Roese <sr@denx.de>
61143f74	4	* Copyright (C) 2020 Marek Behún <kabel@kernel.org>
f61aefc1 SR	5	*/
f61aefc1 SR	6
d678a59d	7	#include <common.h>
9a3b4ceb	8	#include <cpu_func.h>
f61aefc1 SR	9	#include <dm.h>
f61aefc1 SR	10	#include <fdtdec.h>
4a82fca8	11	#include <fdt_support.h>
691d719d	12	#include <init.h>
401d1c4f	13	#include <asm/global_data.h>
cd93d625	14	#include <linux/bitops.h>
b08c8c48	15	#include <linux/libfdt.h>
65375d02	16	#include <linux/sizes.h>
f61aefc1 SR	17	#include <asm/io.h>
	18	#include <asm/system.h>
	19	#include <asm/arch/cpu.h>
	20	#include <asm/arch/soc.h>
	21	#include <asm/armv8/mmu.h>
a129f64f	22	#include <sort.h>
f61aefc1	23
f61aefc1 SR	24	/* Armada 3700 */
	25	#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
	26
	27	#define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
	28	#define MVEBU_XTAL_MODE_MASK BIT(9)
	29	#define MVEBU_XTAL_MODE_OFFS 9
	30	#define MVEBU_XTAL_CLOCK_25MHZ 0x0
	31	#define MVEBU_XTAL_CLOCK_40MHZ 0x1
	32
	33	#define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
	34	#define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
	35
a129f64f MB	36	/* Armada 3700 CPU Address Decoder registers */
	37	#define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00))
	38	#define MVEBU_CPU_DEC_WIN_CTRL(w) \
	39	(MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
	40	#define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0)
	41	#define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf
	42	#define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4
	43	#define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0
	44	#define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2
	45	#define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
	46	#define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
	47	#define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
	48	#define MVEBU_CPU_DEC_WIN_GRANULARITY 16
	49	#define MVEBU_CPU_DEC_WINS 5
65375d02 T	50	#define MVEBU_CPU_DEC_CCI_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
65375d02 T	51	#define MVEBU_CPU_DEC_ROM_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4)
a129f64f	52
65375d02	53	#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 4)
a129f64f MB	54
	55	#define A3700_PTE_BLOCK_NORMAL \
	56	(PTE_BLOCK_MEMTYPE(MT_NORMAL) \| PTE_BLOCK_INNER_SHARE)
	57	#define A3700_PTE_BLOCK_DEVICE \
	58	(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \| PTE_BLOCK_NON_SHARE)
	59
	60	DECLARE_GLOBAL_DATA_PTR;
	61
	62	static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
f61aefc1	63	{
a129f64f MB	64	/*
a129f64f MB	65	* SRAM, MMIO regions
18ab0602	66	* Don't remove this, build_mem_map needs it.
a129f64f MB	67	*/
	68	.phys = SOC_REGS_PHY_BASE,
	69	.virt = SOC_REGS_PHY_BASE,
f61aefc1	70	.size = 0x02000000UL, /* 32MiB internal registers */
a129f64f	71	.attrs = A3700_PTE_BLOCK_DEVICE
92e7a681	72	},
f61aefc1 SR	73	};
	74
	75	struct mm_region *mem_map = mvebu_mem_map;
	76
a129f64f MB	77	static int get_cpu_dec_win(int win, u32 tgt, u32 base, u32 *size)
	78	{
	79	u32 reg;
	80
	81	reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
	82	if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
	83	return -1;
	84
	85	if (tgt) {
	86	reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
	87	reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
	88	*tgt = reg;
	89	}
	90
	91	if (base) {
	92	reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
	93	*base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
	94	}
	95
	96	if (size) {
	97	/*
	98	* Window size is encoded as the number of 1s from LSB to MSB,
	99	* followed by 0s. The number of 1s specifies the size in 64 KiB
	100	* granularity.
	101	*/
	102	reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
	103	*size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
	104	}
	105
	106	return 0;
	107	}
	108
	109	/*
	110	* Builds mem_map according to CPU Address Decoder settings, which were set by
	111	* the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
	112	*/
	113	static void build_mem_map(void)
	114	{
	115	int win, region;
65375d02	116	u32 reg;
a129f64f MB	117
a129f64f MB	118	region = 1;
65375d02 T	119
	120	/* CCI-400 */
	121	reg = readl(MVEBU_CPU_DEC_CCI_BASE);
	122	mvebu_mem_map[region].phys = reg << 20;
	123	mvebu_mem_map[region].virt = reg << 20;
	124	mvebu_mem_map[region].size = SZ_64K;
	125	mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE;
	126	++region;
	127
	128	/* AP BootROM */
	129	reg = readl(MVEBU_CPU_DEC_ROM_BASE);
	130	mvebu_mem_map[region].phys = reg << 20;
	131	mvebu_mem_map[region].virt = reg << 20;
	132	mvebu_mem_map[region].size = SZ_1M;
	133	mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL;
	134	++region;
	135
a129f64f MB	136	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
	137	u32 base, tgt, size;
	138	u64 attrs;
	139
	140	/* skip disabled windows */
	141	if (get_cpu_dec_win(win, &tgt, &base, &size))
	142	continue;
	143
	144	if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
	145	attrs = A3700_PTE_BLOCK_NORMAL;
	146	else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
	147	attrs = A3700_PTE_BLOCK_DEVICE;
	148	else
	149	/* skip windows with other targets */
	150	continue;
	151
	152	mvebu_mem_map[region].phys = base;
	153	mvebu_mem_map[region].virt = base;
	154	mvebu_mem_map[region].size = size;
	155	mvebu_mem_map[region].attrs = attrs;
	156	++region;
	157	}
	158
	159	/* add list terminator */
	160	mvebu_mem_map[region].size = 0;
	161	mvebu_mem_map[region].attrs = 0;
	162	}
	163
	164	void enable_caches(void)
	165	{
a129f64f MB	166	icache_enable();
	167	dcache_enable();
	168	}
	169
	170	int a3700_dram_init(void)
	171	{
	172	int win;
	173
2fb7426c T	174	build_mem_map();
2fb7426c T	175
a129f64f MB	176	gd->ram_size = 0;
	177	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
	178	u32 base, tgt, size;
	179
	180	/* skip disabled windows */
	181	if (get_cpu_dec_win(win, &tgt, &base, &size))
	182	continue;
	183
	184	/* skip non-DRAM windows */
	185	if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
	186	continue;
	187
	188	/*
	189	* It is possible that one image was built for boards with
	190	* different RAM sizes, for example 512 MiB and 1 GiB.
	191	* We therefore try to determine the actual RAM size in the
	192	* window with get_ram_size.
	193	*/
	194	gd->ram_size += get_ram_size((void *)(size_t)base, size);
	195	}
	196
	197	return 0;
	198	}
	199
	200	struct a3700_dram_window {
	201	size_t base, size;
	202	};
	203
	204	static int dram_win_cmp(const void a, const void b)
	205	{
	206	size_t ab, bb;
	207
	208	ab = ((const struct a3700_dram_window *)a)->base;
	209	bb = ((const struct a3700_dram_window *)b)->base;
	210
	211	if (ab < bb)
	212	return -1;
	213	else if (ab > bb)
	214	return 1;
	215	else
	216	return 0;
	217	}
	218
	219	int a3700_dram_init_banksize(void)
	220	{
	221	struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
	222	int bank, win, ndram_wins;
	223	u32 last_end;
	224	size_t size;
	225
	226	ndram_wins = 0;
	227	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
	228	u32 base, tgt, size;
	229
	230	/* skip disabled windows */
	231	if (get_cpu_dec_win(win, &tgt, &base, &size))
	232	continue;
	233
	234	/* skip non-DRAM windows */
	235	if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
	236	continue;
	237
	238	dram_wins[win].base = base;
	239	dram_wins[win].size = size;
240	++ndram_wins;
241	}
242
243	qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);
244
245	bank = 0;
246	last_end = -1;
247
248	for (win = 0; win < ndram_wins; ++win) {
249	/* again determining actual RAM size as in a3700_dram_init */
250	size = get_ram_size((void *)dram_wins[win].base,
251	dram_wins[win].size);
252
253	/*
254	* Check if previous window ends as the current starts. If yes,
255	* merge these windows into one "bank". This is possible by this
256	* simple check thanks to mem_map regions being qsorted in
257	* build_mem_map.
258	*/
259	if (last_end == dram_wins[win].base) {
260	gd->bd->bi_dram[bank - 1].size += size;
261	last_end += size;
262	} else {
263	if (bank == CONFIG_NR_DRAM_BANKS) {
264	printf("Need more CONFIG_NR_DRAM_BANKS\n");
265	return -ENOBUFS;
266	}
267
268	gd->bd->bi_dram[bank].start = dram_wins[win].base;
269	gd->bd->bi_dram[bank].size = size;
270	last_end = dram_wins[win].base + size;
271	++bank;
272	}
273	}
274
275	/*
276	* If there is more place for DRAM BANKS definitions than needed, fill
277	* the rest with zeros.
278	*/
279	for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
280	gd->bd->bi_dram[bank].start = 0;
281	gd->bd->bi_dram[bank].size = 0;
282	}
283
284	return 0;
285	}
286
cb2ddb29 MB	287	static u32 find_pcie_window_base(void)
	288	{
	289	int win;
	290
	291	for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
	292	u32 base, tgt;
	293
	294	/* skip disabled windows */
	295	if (get_cpu_dec_win(win, &tgt, &base, NULL))
	296	continue;
	297
	298	if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
	299	return base;
	300	}
	301
	302	return -1;
	303	}
	304
4a82fca8 T	305	static int fdt_setprop_inplace_u32_partial(void *blob, int node,
	306	const char *name,
	307	u32 idx, u32 val)
	308	{
	309	val = cpu_to_fdt32(val);
	310
	311	return fdt_setprop_inplace_namelen_partial(blob, node, name,
	312	strlen(name),
	313	idx * sizeof(u32),
	314	&val, sizeof(u32));
	315	}
	316
cb2ddb29 MB	317	int a3700_fdt_fix_pcie_regions(void *blob)
cb2ddb29 MB	318	{
1fd54253 T	319	u32 base, lowest_cpu_addr, fix_offset;
1fd54253 T	320	int pci_cells, cpu_cells, size_cells;
cb2ddb29	321	const u32 *ranges;
4a82fca8 T	322	int node, pnode;
	323	int ret, i, len;
	324
	325	base = find_pcie_window_base();
	326	if (base == -1)
	327	return -ENOENT;
cb2ddb29	328
46b679e3	329	node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-3700-pcie");
cb2ddb29 MB	330	if (node < 0)
	331	return node;
	332
	333	ranges = fdt_getprop(blob, node, "ranges", &len);
1fd54253 T	334	if (!ranges \|\| !len \|\| len % sizeof(u32))
1fd54253 T	335	return -EINVAL;
cb2ddb29	336
4a82fca8 T	337	/*
4a82fca8 T	338	* The "ranges" property is an array of
1fd54253 T	339	* { <PCI address> <CPU address> <size in PCI address space> }
	340	* where number of PCI address cells and size cells is stored in the
	341	* "#address-cells" and "#size-cells" properties of the same node
	342	* containing the "ranges" property and number of CPU address cells
	343	* is stored in the parent's "#address-cells" property.
4a82fca8	344	*
1fd54253	345	* All 3 elements can span a diffent number of cells. Fetch them.
4a82fca8 T	346	*/
4a82fca8 T	347	pnode = fdt_parent_offset(blob, node);
1fd54253 T	348	pci_cells = fdt_address_cells(blob, node);
	349	cpu_cells = fdt_address_cells(blob, pnode);
	350	size_cells = fdt_size_cells(blob, node);
cb2ddb29	351
1fd54253 T	352	/* PCI addresses always use 3 cells */
	353	if (pci_cells != 3)
	354	return -EINVAL;
	355
	356	/* CPU addresses on Armada 37xx always use 2 cells */
	357	if (cpu_cells != 2)
	358	return -EINVAL;
	359
	360	for (i = 0; i < len / sizeof(u32);
	361	i += pci_cells + cpu_cells + size_cells) {
	362	/*
	363	* Parent CPU addresses on Armada 37xx are always 32-bit, so
	364	* check that the high word is zero.
	365	*/
	366	if (fdt32_to_cpu(ranges[i + pci_cells]))
	367	return -EINVAL;
	368
	369	if (i == 0 \|\|
	370	fdt32_to_cpu(ranges[i + pci_cells + 1]) < lowest_cpu_addr)
	371	lowest_cpu_addr = fdt32_to_cpu(ranges[i + pci_cells + 1]);
	372	}
cb2ddb29	373
1fd54253 T	374	/* Calculate fixup offset from the lowest (first) CPU address */
1fd54253 T	375	fix_offset = base - lowest_cpu_addr;
cb2ddb29	376
1fd54253	377	/* If fixup offset is zero there is nothing to fix */
cbd7ef70 T	378	if (!fix_offset)
	379	return 0;
	380
4a82fca8	381	/*
1fd54253 T	382	* Fix each CPU address and corresponding PCI address if PCI address
1fd54253 T	383	* is not already remapped (has the same value)
4a82fca8	384	*/
1fd54253 T	385	for (i = 0; i < len / sizeof(u32);
	386	i += pci_cells + cpu_cells + size_cells) {
	387	u32 cpu_addr;
	388	u64 pci_addr;
4a82fca8 T	389	int idx;
4a82fca8 T	390
1fd54253 T	391	/* Fix CPU address */
	392	idx = i + pci_cells + cpu_cells - 1;
	393	cpu_addr = fdt32_to_cpu(ranges[idx]);
4a82fca8	394	ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
1fd54253	395	cpu_addr + fix_offset);
4a82fca8 T	396	if (ret)
	397	return ret;
	398
1fd54253 T	399	/* Fix PCI address only if it isn't remapped (is same as CPU) */
	400	idx = i + pci_cells - 1;
	401	pci_addr = ((u64)fdt32_to_cpu(ranges[idx - 1]) << 32) \|
	402	fdt32_to_cpu(ranges[idx]);
	403	if (cpu_addr != pci_addr)
	404	continue;
	405
4a82fca8	406	ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
1fd54253	407	cpu_addr + fix_offset);
4a82fca8 T	408	if (ret)
	409	return ret;
	410	}
cb2ddb29	411
4a82fca8	412	return 0;
cb2ddb29 MB	413	}
cb2ddb29 MB	414
35b65dd8	415	void reset_cpu(void)
f61aefc1 SR	416	{
	417	/*
	418	* Write magic number of 0x1d1e to North Bridge Warm Reset register
	419	* to trigger warm reset
	420	*/
	421	writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
	422	}
	423
	424	/*
	425	* get_ref_clk
	426	*
	427	* return: reference clock in MHz (25 or 40)
	428	*/
	429	u32 get_ref_clk(void)
	430	{
	431	u32 regval;
	432
	433	regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
	434	MVEBU_XTAL_MODE_OFFS;
	435
	436	if (regval == MVEBU_XTAL_CLOCK_25MHZ)
	437	return 25;
	438	else
	439	return 40;
	440	}