[thirdparty/u-boot.git] / arch / arm / mach-mvebu / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
 */

#include <common.h>
#include <ahci.h>
#include <cpu_func.h>
#include <init.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/mbus.h>
#include <asm/io.h>
#include <asm/pl310.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/spl.h>
#include <sdhci.h>

#define DDR_BASE_CS_OFF(n)	(0x0000 + ((n) << 3))
#define DDR_SIZE_CS_OFF(n)	(0x0004 + ((n) << 3))

static const struct mbus_win windows[] = {
	/* SPI */
	{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
	  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },

	/* BootROM */
	{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
	  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },

#ifdef CONFIG_ARMADA_MSYS
	/* DFX */
	{ MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
#endif
};

/* SPI0 CS0 Flash of size MBUS_SPI_SIZE is mapped to address MBUS_SPI_BASE */
#if CONFIG_ENV_SPI_BUS == 0 && CONFIG_ENV_SPI_CS == 0 && \
    CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE <= MBUS_SPI_SIZE
void *env_sf_get_env_addr(void)
{
	return (void *)MBUS_SPI_BASE + CONFIG_ENV_OFFSET;
}
#endif

void lowlevel_init(void)
{
	/*
	 * Dummy implementation, we only need LOWLEVEL_INIT
	 * on Armada to configure CP15 in start.S / cpu_init_cp15()
	 */
}

#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
void reset_cpu(void)
{
	struct mvebu_system_registers *reg =
		(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;

	writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
	writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
	while (1)
		;
}
#endif

u32 get_boot_device(void)
{
	u32 val;
	u32 boot_device;
	u32 boot_err_mode;
#ifdef CONFIG_ARMADA_38X
	u32 boot_err_code;
#endif

	/*
	 * First check, if UART boot-mode is active. This can only
	 * be done, via the bootrom error register. Here the
	 * MSB marks if the UART mode is active.
	 */
	val = readl(BOOTROM_ERR_REG);
	boot_err_mode = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
	debug("BOOTROM_ERR_REG=0x%08x boot_err_mode=0x%x\n", val, boot_err_mode);
	if (boot_err_mode == BOOTROM_ERR_MODE_UART)
		return BOOT_DEVICE_UART;

#ifdef CONFIG_ARMADA_38X
	/*
	 * If the bootrom error code contains any other than zeros it's an
	 * error condition and the bootROM has fallen back to UART boot
	 */
	boot_err_code = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
	debug("boot_err_code=0x%x\n", boot_err_code);
	if (boot_err_code)
		return BOOT_DEVICE_UART;
#endif

	/*
	 * Now check the SAR register for the strapped boot-device
	 */
	val = readl(CFG_SAR_REG);	/* SAR - Sample At Reset */
	boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
	debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
#ifdef BOOT_FROM_NAND
	if (BOOT_FROM_NAND(boot_device))
		return BOOT_DEVICE_NAND;
#endif
#ifdef BOOT_FROM_MMC
	if (BOOT_FROM_MMC(boot_device))
		return BOOT_DEVICE_MMC1;
#endif
#ifdef BOOT_FROM_UART
	if (BOOT_FROM_UART(boot_device))
		return BOOT_DEVICE_UART;
#endif
#ifdef BOOT_FROM_SATA
	if (BOOT_FROM_SATA(boot_device))
		return BOOT_DEVICE_SATA;
#endif
#ifdef BOOT_FROM_SPI
	if (BOOT_FROM_SPI(boot_device))
		return BOOT_DEVICE_SPI;
#endif
	return BOOT_DEVICE_BOOTROM;
}

#if defined(CONFIG_DISPLAY_CPUINFO)

#if defined(CONFIG_ARMADA_375)
/* SAR frequency values for Armada 375 */
static const struct sar_freq_modes sar_freq_tab[] = {
	{  0,  0x0,  266,  133,  266 },
	{  1,  0x0,  333,  167,  167 },
	{  2,  0x0,  333,  167,  222 },
	{  3,  0x0,  333,  167,  333 },
	{  4,  0x0,  400,  200,  200 },
	{  5,  0x0,  400,  200,  267 },
	{  6,  0x0,  400,  200,  400 },
	{  7,  0x0,  500,  250,  250 },
	{  8,  0x0,  500,  250,  334 },
	{  9,  0x0,  500,  250,  500 },
	{ 10,  0x0,  533,  267,  267 },
	{ 11,  0x0,  533,  267,  356 },
	{ 12,  0x0,  533,  267,  533 },
	{ 13,  0x0,  600,  300,  300 },
	{ 14,  0x0,  600,  300,  400 },
	{ 15,  0x0,  600,  300,  600 },
	{ 16,  0x0,  666,  333,  333 },
	{ 17,  0x0,  666,  333,  444 },
	{ 18,  0x0,  666,  333,  666 },
	{ 19,  0x0,  800,  400,  267 },
	{ 20,  0x0,  800,  400,  400 },
	{ 21,  0x0,  800,  400,  534 },
	{ 22,  0x0,  900,  450,  300 },
	{ 23,  0x0,  900,  450,  450 },
	{ 24,  0x0,  900,  450,  600 },
	{ 25,  0x0, 1000,  500,  500 },
	{ 26,  0x0, 1000,  500,  667 },
	{ 27,  0x0, 1000,  333,  500 },
	{ 28,  0x0,  400,  400,  400 },
	{ 29,  0x0, 1100,  550,  550 },
	{ 0xff, 0xff,    0,   0,   0 }	/* 0xff marks end of array */
};
#elif defined(CONFIG_ARMADA_38X)
/* SAR frequency values for Armada 38x */
static const struct sar_freq_modes sar_freq_tab[] = {
	{  0x0,  0x0,  666,  333, 333 },
	{  0x2,  0x0,  800,  400, 400 },
	{  0x4,  0x0, 1066,  533, 533 },
	{  0x6,  0x0, 1200,  600, 600 },
	{  0x8,  0x0, 1332,  666, 666 },
	{  0xc,  0x0, 1600,  800, 800 },
	{ 0x10,  0x0, 1866,  933, 933 },
	{ 0x13,  0x0, 2000, 1000, 933 },
	{ 0xff, 0xff,    0,    0,   0 }	/* 0xff marks end of array */
};
#elif defined(CONFIG_ARMADA_MSYS)
static const struct sar_freq_modes sar_freq_tab[] = {
	{  0x0,	0x0,  400,  400, 400 },
	{  0x2, 0x0,  667,  333, 667 },
	{  0x3, 0x0,  800,  400, 800 },
	{  0x5, 0x0,  800,  400, 800 },
	{ 0xff, 0xff,    0,   0,   0 }	/* 0xff marks end of array */
};
#else
/* SAR frequency values for Armada XP */
static const struct sar_freq_modes sar_freq_tab[] = {
	{  0xa,  0x5,  800, 400, 400 },
	{  0x1,  0x5, 1066, 533, 533 },
	{  0x2,  0x5, 1200, 600, 600 },
	{  0x2,  0x9, 1200, 600, 400 },
	{  0x3,  0x5, 1333, 667, 667 },
	{  0x4,  0x5, 1500, 750, 750 },
	{  0x4,  0x9, 1500, 750, 500 },
	{  0xb,  0x9, 1600, 800, 533 },
	{  0xb,  0xa, 1600, 800, 640 },
	{  0xb,  0x5, 1600, 800, 800 },
	{ 0xff, 0xff,    0,   0,   0 }	/* 0xff marks end of array */
};
#endif

void get_sar_freq(struct sar_freq_modes *sar_freq)
{
	u32 val;
	u32 freq;
	int i;

#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
	val = readl(CFG_SAR2_REG);	/* SAR - Sample At Reset */
#else
	val = readl(CFG_SAR_REG);	/* SAR - Sample At Reset */
#endif
	freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
#if defined(SAR2_CPU_FREQ_MASK)
	/*
	 * Shift CPU0 clock frequency select bit from SAR2 register
	 * into correct position
	 */
	freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
		 >> SAR2_CPU_FREQ_OFFS) << 3;
#endif
	for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
		if (sar_freq_tab[i].val == freq) {
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
			*sar_freq = sar_freq_tab[i];
			return;
#else
			int k;
			u8 ffc;

			ffc = (val & SAR_FFC_FREQ_MASK) >>
				SAR_FFC_FREQ_OFFS;
			for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
				if (sar_freq_tab[k].ffc == ffc) {
					*sar_freq = sar_freq_tab[k];
					return;
				}
			}
			i = k;
#endif
		}
	}

	/* SAR value not found, return 0 for frequencies */
	*sar_freq = sar_freq_tab[i - 1];
}

int print_cpuinfo(void)
{
	u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
	u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
	struct sar_freq_modes sar_freq;

	puts("SoC:   ");

	switch (devid) {
	case SOC_MV78230_ID:
		puts("MV78230-");
		break;
	case SOC_MV78260_ID:
		puts("MV78260-");
		break;
	case SOC_MV78460_ID:
		puts("MV78460-");
		break;
	case SOC_88F6720_ID:
		puts("MV88F6720-");
		break;
	case SOC_88F6810_ID:
		puts("MV88F6810-");
		break;
	case SOC_88F6820_ID:
		puts("MV88F6820-");
		break;
	case SOC_88F6828_ID:
		puts("MV88F6828-");
		break;
	case SOC_98DX3236_ID:
		puts("98DX3236-");
		break;
	case SOC_98DX3336_ID:
		puts("98DX3336-");
		break;
	case SOC_98DX4251_ID:
		puts("98DX4251-");
		break;
	default:
		puts("Unknown-");
		break;
	}

	switch (devid) {
	case SOC_MV78230_ID:
	case SOC_MV78260_ID:
	case SOC_MV78460_ID:
		switch (revid) {
		case 1:
			puts("A0");
			break;
		case 2:
			puts("B0");
			break;
		default:
			printf("?? (%x)", revid);
			break;
		}
		break;

	case SOC_88F6720_ID:
		switch (revid) {
		case MV_88F67XX_A0_ID:
			puts("A0");
			break;
		default:
			printf("?? (%x)", revid);
			break;
		}
		break;

	case SOC_88F6810_ID:
	case SOC_88F6820_ID:
	case SOC_88F6828_ID:
		switch (revid) {
		case MV_88F68XX_Z1_ID:
			puts("Z1");
			break;
		case MV_88F68XX_A0_ID:
			puts("A0");
			break;
		case MV_88F68XX_B0_ID:
			puts("B0");
			break;
		default:
			printf("?? (%x)", revid);
			break;
		}
		break;

	case SOC_98DX3236_ID:
	case SOC_98DX3336_ID:
	case SOC_98DX4251_ID:
		switch (revid) {
		case 3:
			puts("A0");
			break;
		case 4:
			puts("A1");
			break;
		default:
			printf("?? (%x)", revid);
			break;
		}
		break;

	default:
		printf("?? (%x)", revid);
		break;
	}

	get_sar_freq(&sar_freq);
	printf(" at %d MHz\n", sar_freq.p_clk);

	return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

/*
 * This function initialize Controller DRAM Fastpath windows.
 * It takes the CS size information from the 0x1500 scratch registers
 * and sets the correct windows sizes and base addresses accordingly.
 *
 * These values are set in the scratch registers by the Marvell
 * DDR3 training code, which is executed by the SPL before the
 * main payload (U-Boot) is executed.
 */
static void update_sdram_window_sizes(void)
{
	u64 base = 0;
	u32 size, temp;
	int i;

	for (i = 0; i < SDRAM_MAX_CS; i++) {
		size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
		if (size != 0) {
			size |= ~(SDRAM_ADDR_MASK);

			/* Set Base Address */
			temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
			writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));

			/*
			 * Check if out of max window size and resize
			 * the window
			 */
			temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
				~(SDRAM_ADDR_MASK)) | 1;
			temp |= (size & SDRAM_ADDR_MASK);
			writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));

			base += ((u64)size + 1);
		} else {
			/*
			 * Disable window if not used, otherwise this
			 * leads to overlapping enabled windows with
			 * pretty strange results
			 */
			clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
		}
	}
}

#ifdef CONFIG_ARCH_CPU_INIT
#define MV_USB_PHY_BASE			(MVEBU_AXP_USB_BASE + 0x800)
#define MV_USB_PHY_PLL_REG(reg)		(MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
#define MV_USB_X3_BASE(addr)		(MVEBU_AXP_USB_BASE | BIT(11) | \
					 (((addr) & 0xF) << 6))
#define MV_USB_X3_PHY_CHANNEL(dev, reg)	(MV_USB_X3_BASE((dev) + 1) |	\
					 (((reg) & 0xF) << 2))

static void setup_usb_phys(void)
{
	int dev;

	/*
	 * USB PLL init
	 */

	/* Setup PLL frequency */
	/* USB REF frequency = 25 MHz */
	clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);

	/* Power up PLL and PHY channel */
	setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));

	/* Assert VCOCAL_START */
	setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));

	mdelay(1);

	/*
	 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
	 */

	for (dev = 0; dev < 3; dev++) {
		setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));

		/* Assert REG_RCAL_START in channel REG 1 */
		setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
		udelay(40);
		clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
	}
}

/*
 * This function is not called from the SPL U-Boot version
 */
int arch_cpu_init(void)
{
	/*
	 * We need to call mvebu_mbus_probe() before calling
	 * update_sdram_window_sizes() as it disables all previously
	 * configured mbus windows and then configures them as
	 * required for U-Boot. Calling update_sdram_window_sizes()
	 * without this configuration will not work, as the internal
	 * registers can't be accessed reliably because of potenial
	 * double mapping.
	 * After updating the SDRAM access windows we need to call
	 * mvebu_mbus_probe() again, as this now correctly configures
	 * the SDRAM areas that are later used by the MVEBU drivers
	 * (e.g. USB, NETA).
	 */

	/*
	 * First disable all windows
	 */
	mvebu_mbus_probe(NULL, 0);

	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
		/*
		 * Now the SDRAM access windows can be reconfigured using
		 * the information in the SDRAM scratch pad registers
		 */
		update_sdram_window_sizes();
	}

	/*
	 * Finally the mbus windows can be configured with the
	 * updated SDRAM sizes
	 */
	mvebu_mbus_probe(windows, ARRAY_SIZE(windows));

	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
		/* Enable GBE0, GBE1, LCD and NFC PUP */
		clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
				GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
				NAND_PUP_EN | SPI_PUP_EN);

		/* Configure USB PLL and PHYs on AXP */
		setup_usb_phys();
	}

	/* Enable NAND and NAND arbiter */
	clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);

	/* Disable MBUS error propagation */
	clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);

	return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */

u32 mvebu_get_nand_clock(void)
{
	u32 reg;

	if (IS_ENABLED(CONFIG_ARMADA_38X))
		reg = MVEBU_DFX_DIV_CLK_CTRL(1);
	else if (IS_ENABLED(CONFIG_ARMADA_MSYS))
		reg = MVEBU_DFX_DIV_CLK_CTRL(8);
	else
		reg = MVEBU_CORE_DIV_CLK_CTRL(1);

	return CONFIG_SYS_MVEBU_PLL_CLOCK /
		((readl(reg) &
		  NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
}

#if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
int board_mmc_init(struct bd_info *bis)
{
	mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
		    SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);

	return 0;
}
#endif

#define AHCI_VENDOR_SPECIFIC_0_ADDR	0xa0
#define AHCI_VENDOR_SPECIFIC_0_DATA	0xa4

#define AHCI_WINDOW_CTRL(win)		(0x60 + ((win) << 4))
#define AHCI_WINDOW_BASE(win)		(0x64 + ((win) << 4))
#define AHCI_WINDOW_SIZE(win)		(0x68 + ((win) << 4))

static void ahci_mvebu_mbus_config(void __iomem *base)
{
	const struct mbus_dram_target_info *dram;
	int i;

	/* mbus is not initialized in SPL; keep the ROM settings */
	if (IS_ENABLED(CONFIG_SPL_BUILD))
		return;

	dram = mvebu_mbus_dram_info();

	for (i = 0; i < 4; i++) {
		writel(0, base + AHCI_WINDOW_CTRL(i));
		writel(0, base + AHCI_WINDOW_BASE(i));
		writel(0, base + AHCI_WINDOW_SIZE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		writel((cs->mbus_attr << 8) |
		       (dram->mbus_dram_target_id << 4) | 1,
		       base + AHCI_WINDOW_CTRL(i));
		writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
		writel(((cs->size - 1) & 0xffff0000),
		       base + AHCI_WINDOW_SIZE(i));
	}
}

static void ahci_mvebu_regret_option(void __iomem *base)
{
	/*
	 * Enable the regret bit to allow the SATA unit to regret a
	 * request that didn't receive an acknowlegde and avoid a
	 * deadlock
	 */
	writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
	writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
}

int board_ahci_enable(void)
{
	ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
	ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);

	return 0;
}

#ifdef CONFIG_USB_XHCI_MVEBU
#define USB3_MAX_WINDOWS        4
#define USB3_WIN_CTRL(w)        (0x0 + ((w) * 8))
#define USB3_WIN_BASE(w)        (0x4 + ((w) * 8))

static void xhci_mvebu_mbus_config(void __iomem *base,
			const struct mbus_dram_target_info *dram)
{
	int i;

	for (i = 0; i < USB3_MAX_WINDOWS; i++) {
		writel(0, base + USB3_WIN_CTRL(i));
		writel(0, base + USB3_WIN_BASE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		/* Write size, attributes and target id to control register */
		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) | 1,
			base + USB3_WIN_CTRL(i));

		/* Write base address to base register */
		writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
	}
}

int board_xhci_enable(fdt_addr_t base)
{
	const struct mbus_dram_target_info *dram;

	printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);

	dram = mvebu_mbus_dram_info();
	xhci_mvebu_mbus_config((void __iomem *)base, dram);

	return 0;
}
#endif

void enable_caches(void)
{
	/* Avoid problem with e.g. neta ethernet driver */
	invalidate_dcache_all();

	/*
	 * Armada 375 still has some problems with d-cache enabled in the
	 * ethernet driver (mvpp2). So lets keep the d-cache disabled
	 * until this is solved.
	 */
	if (!IS_ENABLED(CONFIG_ARMADA_375)) {
		/* Enable D-cache. I-cache is already enabled in start.S */
		dcache_enable();
	}
}

void v7_outer_cache_enable(void)
{
	struct pl310_regs *const pl310 =
		(struct pl310_regs *)CFG_SYS_PL310_BASE;

	/* The L2 cache is already disabled at this point */

	/*
	 * For now L2 cache will be enabled only for Armada XP and Armada 38x.
	 * It can be enabled also for other SoCs after testing that it works fine.
	 */
	if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X))
		return;

	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
		u32 u;

		/*
		 * For Aurora cache in no outer mode, enable via the CP15
		 * coprocessor broadcasting of cache commands to L2.
		 */
		asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
		u |= BIT(8);		/* Set the FW bit */
		asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));

		isb();
	}

	/* Enable the L2 cache */
	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}

void v7_outer_cache_disable(void)
{
	struct pl310_regs *const pl310 =
		(struct pl310_regs *)CFG_SYS_PL310_BASE;

	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
41e5ee54	2	/*
d35831f6	3	* Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
41e5ee54 SR	4	*/
41e5ee54 SR	5
d678a59d	6	#include <common.h>
4d991cb3	7	#include <ahci.h>
9edefc27	8	#include <cpu_func.h>
691d719d	9	#include <init.h>
cd93d625	10	#include <linux/bitops.h>
c05ed00a	11	#include <linux/delay.h>
4d991cb3	12	#include <linux/mbus.h>
41e5ee54	13	#include <asm/io.h>
5730360e	14	#include <asm/pl310.h>
41e5ee54 SR	15	#include <asm/arch/cpu.h>
41e5ee54 SR	16	#include <asm/arch/soc.h>
dc595e3e	17	#include <asm/spl.h>
7f1adcd7	18	#include <sdhci.h>
41e5ee54 SR	19
	20	#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
	21	#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
	22
b120519d	23	static const struct mbus_win windows[] = {
41e5ee54	24	/* SPI */
8ed20d65 SR	25	{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
8ed20d65 SR	26	CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
41e5ee54	27
7c406797	28	/* BootROM */
8ed20d65 SR	29	{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
8ed20d65 SR	30	CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
0d0df46e CP	31
	32	#ifdef CONFIG_ARMADA_MSYS
	33	/* DFX */
	34	{ MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
	35	#endif
41e5ee54 SR	36	};
41e5ee54 SR	37
056808a4 T	38	/* SPI0 CS0 Flash of size MBUS_SPI_SIZE is mapped to address MBUS_SPI_BASE */
	39	#if CONFIG_ENV_SPI_BUS == 0 && CONFIG_ENV_SPI_CS == 0 && \
	40	CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE <= MBUS_SPI_SIZE
	41	void *env_sf_get_env_addr(void)
	42	{
	43	return (void *)MBUS_SPI_BASE + CONFIG_ENV_OFFSET;
	44	}
	45	#endif
	46
42cc034f SR	47	void lowlevel_init(void)
	48	{
	49	/*
	50	* Dummy implementation, we only need LOWLEVEL_INIT
	51	* on Armada to configure CP15 in start.S / cpu_init_cp15()
	52	*/
	53	}
	54
0c350a67	55	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
35b65dd8	56	void reset_cpu(void)
41e5ee54 SR	57	{
	58	struct mvebu_system_registers *reg =
	59	(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
	60
	61	writel(readl(&reg->rstoutn_mask) \| 1, &reg->rstoutn_mask);
	62	writel(readl(&reg->sys_soft_rst) \| 1, &reg->sys_soft_rst);
	63	while (1)
	64	;
	65	}
0c350a67	66	#endif
41e5ee54	67
dc595e3e MB	68	u32 get_boot_device(void)
	69	{
	70	u32 val;
	71	u32 boot_device;
785f5379 T	72	u32 boot_err_mode;
	73	#ifdef CONFIG_ARMADA_38X
	74	u32 boot_err_code;
	75	#endif
dc595e3e MB	76
dc595e3e MB	77	/*
48cf96fb TR	78	* First check, if UART boot-mode is active. This can only
	79	* be done, via the bootrom error register. Here the
	80	* MSB marks if the UART mode is active.
	81	*/
4e4fff7d	82	val = readl(BOOTROM_ERR_REG);
785f5379 T	83	boot_err_mode = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
	84	debug("BOOTROM_ERR_REG=0x%08x boot_err_mode=0x%x\n", val, boot_err_mode);
	85	if (boot_err_mode == BOOTROM_ERR_MODE_UART)
dc595e3e MB	86	return BOOT_DEVICE_UART;
	87
	88	#ifdef CONFIG_ARMADA_38X
	89	/*
48cf96fb TR	90	* If the bootrom error code contains any other than zeros it's an
	91	* error condition and the bootROM has fallen back to UART boot
	92	*/
785f5379 T	93	boot_err_code = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
	94	debug("boot_err_code=0x%x\n", boot_err_code);
	95	if (boot_err_code)
dc595e3e MB	96	return BOOT_DEVICE_UART;
	97	#endif
	98
	99	/*
48cf96fb TR	100	* Now check the SAR register for the strapped boot-device
48cf96fb TR	101	*/
9dbe356e	102	val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */
dc595e3e MB	103	boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
dc595e3e MB	104	debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
dc595e3e	105	#ifdef BOOT_FROM_NAND
7ba084c7	106	if (BOOT_FROM_NAND(boot_device))
dc595e3e MB	107	return BOOT_DEVICE_NAND;
	108	#endif
	109	#ifdef BOOT_FROM_MMC
7ba084c7	110	if (BOOT_FROM_MMC(boot_device))
dc595e3e MB	111	return BOOT_DEVICE_MMC1;
dc595e3e MB	112	#endif
7ba084c7 T	113	#ifdef BOOT_FROM_UART
7ba084c7 T	114	if (BOOT_FROM_UART(boot_device))
dc595e3e	115	return BOOT_DEVICE_UART;
7ba084c7	116	#endif
dc595e3e	117	#ifdef BOOT_FROM_SATA
7ba084c7	118	if (BOOT_FROM_SATA(boot_device))
dc595e3e MB	119	return BOOT_DEVICE_SATA;
dc595e3e MB	120	#endif
7ba084c7 T	121	#ifdef BOOT_FROM_SPI
7ba084c7 T	122	if (BOOT_FROM_SPI(boot_device))
dc595e3e	123	return BOOT_DEVICE_SPI;
7ba084c7 T	124	#endif
7ba084c7 T	125	return BOOT_DEVICE_BOOTROM;
dc595e3e MB	126	}
dc595e3e MB	127
41e5ee54	128	#if defined(CONFIG_DISPLAY_CPUINFO)
d718bf2c	129
09e89ab4 SR	130	#if defined(CONFIG_ARMADA_375)
	131	/* SAR frequency values for Armada 375 */
	132	static const struct sar_freq_modes sar_freq_tab[] = {
	133	{ 0, 0x0, 266, 133, 266 },
	134	{ 1, 0x0, 333, 167, 167 },
	135	{ 2, 0x0, 333, 167, 222 },
	136	{ 3, 0x0, 333, 167, 333 },
	137	{ 4, 0x0, 400, 200, 200 },
	138	{ 5, 0x0, 400, 200, 267 },
	139	{ 6, 0x0, 400, 200, 400 },
	140	{ 7, 0x0, 500, 250, 250 },
	141	{ 8, 0x0, 500, 250, 334 },
	142	{ 9, 0x0, 500, 250, 500 },
	143	{ 10, 0x0, 533, 267, 267 },
	144	{ 11, 0x0, 533, 267, 356 },
	145	{ 12, 0x0, 533, 267, 533 },
	146	{ 13, 0x0, 600, 300, 300 },
	147	{ 14, 0x0, 600, 300, 400 },
	148	{ 15, 0x0, 600, 300, 600 },
	149	{ 16, 0x0, 666, 333, 333 },
	150	{ 17, 0x0, 666, 333, 444 },
	151	{ 18, 0x0, 666, 333, 666 },
	152	{ 19, 0x0, 800, 400, 267 },
	153	{ 20, 0x0, 800, 400, 400 },
	154	{ 21, 0x0, 800, 400, 534 },
	155	{ 22, 0x0, 900, 450, 300 },
	156	{ 23, 0x0, 900, 450, 450 },
	157	{ 24, 0x0, 900, 450, 600 },
	158	{ 25, 0x0, 1000, 500, 500 },
	159	{ 26, 0x0, 1000, 500, 667 },
	160	{ 27, 0x0, 1000, 333, 500 },
	161	{ 28, 0x0, 400, 400, 400 },
	162	{ 29, 0x0, 1100, 550, 550 },
	163	{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
	164	};
	165	#elif defined(CONFIG_ARMADA_38X)
d35831f6	166	/* SAR frequency values for Armada 38x */
a9fc5a24	167	static const struct sar_freq_modes sar_freq_tab[] = {
0a91e1cc CP	168	{ 0x0, 0x0, 666, 333, 333 },
	169	{ 0x2, 0x0, 800, 400, 400 },
	170	{ 0x4, 0x0, 1066, 533, 533 },
	171	{ 0x6, 0x0, 1200, 600, 600 },
	172	{ 0x8, 0x0, 1332, 666, 666 },
	173	{ 0xc, 0x0, 1600, 800, 800 },
	174	{ 0x10, 0x0, 1866, 933, 933 },
	175	{ 0x13, 0x0, 2000, 1000, 933 },
	176	{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
d718bf2c	177	};
0d0df46e CP	178	#elif defined(CONFIG_ARMADA_MSYS)
	179	static const struct sar_freq_modes sar_freq_tab[] = {
	180	{ 0x0, 0x0, 400, 400, 400 },
	181	{ 0x2, 0x0, 667, 333, 667 },
	182	{ 0x3, 0x0, 800, 400, 800 },
	183	{ 0x5, 0x0, 800, 400, 800 },
	184	{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
	185	};
d718bf2c	186	#else
d35831f6	187	/* SAR frequency values for Armada XP */
a9fc5a24	188	static const struct sar_freq_modes sar_freq_tab[] = {
d718bf2c SR	189	{ 0xa, 0x5, 800, 400, 400 },
	190	{ 0x1, 0x5, 1066, 533, 533 },
	191	{ 0x2, 0x5, 1200, 600, 600 },
	192	{ 0x2, 0x9, 1200, 600, 400 },
	193	{ 0x3, 0x5, 1333, 667, 667 },
	194	{ 0x4, 0x5, 1500, 750, 750 },
	195	{ 0x4, 0x9, 1500, 750, 500 },
	196	{ 0xb, 0x9, 1600, 800, 533 },
	197	{ 0xb, 0xa, 1600, 800, 640 },
	198	{ 0xb, 0x5, 1600, 800, 800 },
	199	{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
	200	};
	201	#endif
	202
	203	void get_sar_freq(struct sar_freq_modes *sar_freq)
	204	{
	205	u32 val;
	206	u32 freq;
	207	int i;
	208
0d0df46e	209	#if defined(CONFIG_ARMADA_375) \|\| defined(CONFIG_ARMADA_MSYS)
f9932d38	210	val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */
09e89ab4	211	#else
9dbe356e	212	val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */
09e89ab4	213	#endif
d718bf2c	214	freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
09e89ab4	215	#if defined(SAR2_CPU_FREQ_MASK)
d718bf2c SR	216	/*
	217	* Shift CPU0 clock frequency select bit from SAR2 register
	218	* into correct position
	219	*/
f9932d38	220	freq \|= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
d718bf2c SR	221	>> SAR2_CPU_FREQ_OFFS) << 3;
	222	#endif
	223	for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
	224	if (sar_freq_tab[i].val == freq) {
0d0df46e	225	#if defined(CONFIG_ARMADA_375) \|\| defined(CONFIG_ARMADA_38X) \|\| defined(CONFIG_ARMADA_MSYS)
d718bf2c SR	226	*sar_freq = sar_freq_tab[i];
	227	return;
	228	#else
	229	int k;
	230	u8 ffc;
	231
	232	ffc = (val & SAR_FFC_FREQ_MASK) >>
	233	SAR_FFC_FREQ_OFFS;
	234	for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
	235	if (sar_freq_tab[k].ffc == ffc) {
	236	*sar_freq = sar_freq_tab[k];
	237	return;
	238	}
	239	}
	240	i = k;
	241	#endif
	242	}
	243	}
	244
	245	/* SAR value not found, return 0 for frequencies */
	246	*sar_freq = sar_freq_tab[i - 1];
	247	}
	248
41e5ee54 SR	249	int print_cpuinfo(void)
	250	{
	251	u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
	252	u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
d718bf2c	253	struct sar_freq_modes sar_freq;
41e5ee54 SR	254
	255	puts("SoC: ");
	256
	257	switch (devid) {
6202953d PS	258	case SOC_MV78230_ID:
	259	puts("MV78230-");
	260	break;
bf0db8b8 SR	261	case SOC_MV78260_ID:
	262	puts("MV78260-");
	263	break;
41e5ee54 SR	264	case SOC_MV78460_ID:
	265	puts("MV78460-");
	266	break;
09e89ab4 SR	267	case SOC_88F6720_ID:
	268	puts("MV88F6720-");
	269	break;
9c6d3b7b SR	270	case SOC_88F6810_ID:
9c6d3b7b SR	271	puts("MV88F6810-");
41e5ee54	272	break;
9c6d3b7b SR	273	case SOC_88F6820_ID:
9c6d3b7b SR	274	puts("MV88F6820-");
41e5ee54	275	break;
9c6d3b7b SR	276	case SOC_88F6828_ID:
9c6d3b7b SR	277	puts("MV88F6828-");
41e5ee54	278	break;
0f8031a3 CP	279	case SOC_98DX3236_ID:
	280	puts("98DX3236-");
	281	break;
	282	case SOC_98DX3336_ID:
	283	puts("98DX3336-");
	284	break;
	285	case SOC_98DX4251_ID:
	286	puts("98DX4251-");
	287	break;
41e5ee54	288	default:
9c6d3b7b	289	puts("Unknown-");
41e5ee54 SR	290	break;
	291	}
	292
3308933d T	293	switch (devid) {
	294	case SOC_MV78230_ID:
	295	case SOC_MV78260_ID:
	296	case SOC_MV78460_ID:
9c6d3b7b SR	297	switch (revid) {
9c6d3b7b SR	298	case 1:
d718bf2c	299	puts("A0");
9c6d3b7b SR	300	break;
9c6d3b7b SR	301	case 2:
d718bf2c	302	puts("B0");
9c6d3b7b SR	303	break;
9c6d3b7b SR	304	default:
d718bf2c	305	printf("?? (%x)", revid);
9c6d3b7b SR	306	break;
9c6d3b7b SR	307	}
3308933d	308	break;
9c6d3b7b	309
3308933d	310	case SOC_88F6720_ID:
09e89ab4 SR	311	switch (revid) {
	312	case MV_88F67XX_A0_ID:
	313	puts("A0");
	314	break;
	315	default:
	316	printf("?? (%x)", revid);
	317	break;
	318	}
3308933d	319	break;
09e89ab4	320
3308933d T	321	case SOC_88F6810_ID:
	322	case SOC_88F6820_ID:
	323	case SOC_88F6828_ID:
9c6d3b7b SR	324	switch (revid) {
9c6d3b7b SR	325	case MV_88F68XX_Z1_ID:
d718bf2c	326	puts("Z1");
9c6d3b7b SR	327	break;
9c6d3b7b SR	328	case MV_88F68XX_A0_ID:
d718bf2c	329	puts("A0");
9c6d3b7b	330	break;
d997ad03 CP	331	case MV_88F68XX_B0_ID:
	332	puts("B0");
	333	break;
9c6d3b7b	334	default:
d718bf2c	335	printf("?? (%x)", revid);
9c6d3b7b SR	336	break;
9c6d3b7b SR	337	}
3308933d	338	break;
9c6d3b7b	339
3308933d T	340	case SOC_98DX3236_ID:
	341	case SOC_98DX3336_ID:
	342	case SOC_98DX4251_ID:
0d0df46e CP	343	switch (revid) {
	344	case 3:
	345	puts("A0");
	346	break;
	347	case 4:
	348	puts("A1");
	349	break;
	350	default:
	351	printf("?? (%x)", revid);
	352	break;
	353	}
3308933d T	354	break;
	355
	356	default:
	357	printf("?? (%x)", revid);
	358	break;
0d0df46e CP	359	}
0d0df46e CP	360
d718bf2c SR	361	get_sar_freq(&sar_freq);
	362	printf(" at %d MHz\n", sar_freq.p_clk);
	363
41e5ee54 SR	364	return 0;
	365	}
	366	#endif /* CONFIG_DISPLAY_CPUINFO */
	367
	368	/*
	369	* This function initialize Controller DRAM Fastpath windows.
	370	* It takes the CS size information from the 0x1500 scratch registers
	371	* and sets the correct windows sizes and base addresses accordingly.
	372	*
	373	* These values are set in the scratch registers by the Marvell
1670a154 CP	374	* DDR3 training code, which is executed by the SPL before the
1670a154 CP	375	* main payload (U-Boot) is executed.
41e5ee54 SR	376	*/
	377	static void update_sdram_window_sizes(void)
	378	{
	379	u64 base = 0;
	380	u32 size, temp;
	381	int i;
	382
	383	for (i = 0; i < SDRAM_MAX_CS; i++) {
	384	size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
	385	if (size != 0) {
	386	size \|= ~(SDRAM_ADDR_MASK);
	387
	388	/* Set Base Address */
	389	temp = (base & 0xFF000000ll) \| ((base >> 32) & 0xF);
	390	writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
	391
	392	/*
	393	* Check if out of max window size and resize
	394	* the window
	395	*/
	396	temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
	397	~(SDRAM_ADDR_MASK)) \| 1;
	398	temp \|= (size & SDRAM_ADDR_MASK);
	399	writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
	400
	401	base += ((u64)size + 1);
	402	} else {
	403	/*
	404	* Disable window if not used, otherwise this
	405	* leads to overlapping enabled windows with
	406	* pretty strange results
	407	*/
	408	clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
	409	}
	410	}
	411	}
	412
	413	#ifdef CONFIG_ARCH_CPU_INIT
dee40d26 SR	414	#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
	415	#define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE \| (((reg) & 0xF) << 2))
	416	#define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE \| BIT(11) \| \
	417	(((addr) & 0xF) << 6))
	418	#define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) \| \
	419	(((reg) & 0xF) << 2))
	420
	421	static void setup_usb_phys(void)
	422	{
	423	int dev;
	424
	425	/*
	426	* USB PLL init
	427	*/
	428
	429	/* Setup PLL frequency */
	430	/* USB REF frequency = 25 MHz */
	431	clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
	432
	433	/* Power up PLL and PHY channel */
ab8a4c6a	434	setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
dee40d26 SR	435
dee40d26 SR	436	/* Assert VCOCAL_START */
ab8a4c6a	437	setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
dee40d26 SR	438
	439	mdelay(1);
	440
	441	/*
	442	* USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
	443	*/
	444
	445	for (dev = 0; dev < 3; dev++) {
ab8a4c6a	446	setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
dee40d26 SR	447
dee40d26 SR	448	/* Assert REG_RCAL_START in channel REG 1 */
ab8a4c6a	449	setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
dee40d26	450	udelay(40);
ab8a4c6a	451	clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
dee40d26 SR	452	}
dee40d26 SR	453	}
e1b078e0	454
f4e6ec7d SR	455	/*
	456	* This function is not called from the SPL U-Boot version
	457	*/
41e5ee54 SR	458	int arch_cpu_init(void)
41e5ee54 SR	459	{
41e5ee54 SR	460	/*
	461	* We need to call mvebu_mbus_probe() before calling
	462	* update_sdram_window_sizes() as it disables all previously
	463	* configured mbus windows and then configures them as
	464	* required for U-Boot. Calling update_sdram_window_sizes()
	465	* without this configuration will not work, as the internal
	466	* registers can't be accessed reliably because of potenial
	467	* double mapping.
	468	* After updating the SDRAM access windows we need to call
	469	* mvebu_mbus_probe() again, as this now correctly configures
	470	* the SDRAM areas that are later used by the MVEBU drivers
	471	* (e.g. USB, NETA).
	472	*/
	473
	474	/*
	475	* First disable all windows
	476	*/
	477	mvebu_mbus_probe(NULL, 0);
	478
3308933d	479	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
9c6d3b7b SR	480	/*
	481	* Now the SDRAM access windows can be reconfigured using
	482	* the information in the SDRAM scratch pad registers
	483	*/
	484	update_sdram_window_sizes();
	485	}
41e5ee54 SR	486
	487	/*
	488	* Finally the mbus windows can be configured with the
	489	* updated SDRAM sizes
	490	*/
	491	mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
	492
3308933d	493	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
2a0b7dc3 SR	494	/* Enable GBE0, GBE1, LCD and NFC PUP */
	495	clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
	496	GE0_PUP_EN \| GE1_PUP_EN \| LCD_PUP_EN \|
	497	NAND_PUP_EN \| SPI_PUP_EN);
dee40d26 SR	498
	499	/* Configure USB PLL and PHYs on AXP */
	500	setup_usb_phys();
2a0b7dc3 SR	501	}
	502
	503	/* Enable NAND and NAND arbiter */
	504	clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN \| NAND_ARBITER_EN);
	505
501c098a SR	506	/* Disable MBUS error propagation */
	507	clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
	508
41e5ee54 SR	509	return 0;
	510	}
	511	#endif /* CONFIG_ARCH_CPU_INIT */
	512
2a0b7dc3 SR	513	u32 mvebu_get_nand_clock(void)
2a0b7dc3 SR	514	{
d7b4731e CP	515	u32 reg;
d7b4731e CP	516
3308933d	517	if (IS_ENABLED(CONFIG_ARMADA_38X))
d7b4731e	518	reg = MVEBU_DFX_DIV_CLK_CTRL(1);
3308933d	519	else if (IS_ENABLED(CONFIG_ARMADA_MSYS))
689f9cf6	520	reg = MVEBU_DFX_DIV_CLK_CTRL(8);
d7b4731e CP	521	else
	522	reg = MVEBU_CORE_DIV_CLK_CTRL(1);
	523
2a0b7dc3	524	return CONFIG_SYS_MVEBU_PLL_CLOCK /
d7b4731e	525	((readl(reg) &
2a0b7dc3 SR	526	NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
	527	}
	528
4ec9dd40	529	#if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
b75d8dc5	530	int board_mmc_init(struct bd_info *bis)
7f1adcd7 SR	531	{
	532	mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
	533	SDHCI_QUIRK_32BIT_DMA_ADDR \| SDHCI_QUIRK_WAIT_SEND_CMD);
	534
	535	return 0;
	536	}
	537	#endif
	538
4d991cb3 SR	539	#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
	540	#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
	541
	542	#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
	543	#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
	544	#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
	545
	546	static void ahci_mvebu_mbus_config(void __iomem *base)
	547	{
	548	const struct mbus_dram_target_info *dram;
	549	int i;
	550
f0aa1254 BS	551	/* mbus is not initialized in SPL; keep the ROM settings */
	552	if (IS_ENABLED(CONFIG_SPL_BUILD))
	553	return;
	554
4d991cb3 SR	555	dram = mvebu_mbus_dram_info();
	556
	557	for (i = 0; i < 4; i++) {
	558	writel(0, base + AHCI_WINDOW_CTRL(i));
	559	writel(0, base + AHCI_WINDOW_BASE(i));
	560	writel(0, base + AHCI_WINDOW_SIZE(i));
	561	}
	562
	563	for (i = 0; i < dram->num_cs; i++) {
	564	const struct mbus_dram_window *cs = dram->cs + i;
	565
	566	writel((cs->mbus_attr << 8) \|
	567	(dram->mbus_dram_target_id << 4) \| 1,
	568	base + AHCI_WINDOW_CTRL(i));
	569	writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
	570	writel(((cs->size - 1) & 0xffff0000),
	571	base + AHCI_WINDOW_SIZE(i));
	572	}
	573	}
	574
	575	static void ahci_mvebu_regret_option(void __iomem *base)
	576	{
	577	/*
	578	* Enable the regret bit to allow the SATA unit to regret a
	579	* request that didn't receive an acknowlegde and avoid a
	580	* deadlock
	581	*/
	582	writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
	583	writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
	584	}
	585
4b11e5f6	586	int board_ahci_enable(void)
4d991cb3	587	{
4d991cb3 SR	588	ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
4d991cb3 SR	589	ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
4b11e5f6 BS	590
	591	return 0;
	592	}
	593
78aa018f JN	594	#ifdef CONFIG_USB_XHCI_MVEBU
	595	#define USB3_MAX_WINDOWS 4
	596	#define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
	597	#define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
	598
	599	static void xhci_mvebu_mbus_config(void __iomem *base,
	600	const struct mbus_dram_target_info *dram)
	601	{
	602	int i;
	603
	604	for (i = 0; i < USB3_MAX_WINDOWS; i++) {
	605	writel(0, base + USB3_WIN_CTRL(i));
	606	writel(0, base + USB3_WIN_BASE(i));
	607	}
	608
	609	for (i = 0; i < dram->num_cs; i++) {
	610	const struct mbus_dram_window *cs = dram->cs + i;
	611
	612	/* Write size, attributes and target id to control register */
	613	writel(((cs->size - 1) & 0xffff0000) \| (cs->mbus_attr << 8) \|
	614	(dram->mbus_dram_target_id << 4) \| 1,
	615	base + USB3_WIN_CTRL(i));
	616
	617	/* Write base address to base register */
	618	writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
	619	}
	620	}
	621
	622	int board_xhci_enable(fdt_addr_t base)
	623	{
	624	const struct mbus_dram_target_info *dram;
	625
84404d81	626	printf("MVEBU XHCI INIT controller @ 0x%llx\n", (fdt64_t)base);
78aa018f JN	627
	628	dram = mvebu_mbus_dram_info();
	629	xhci_mvebu_mbus_config((void __iomem *)base, dram);
	630
	631	return 0;
	632	}
	633	#endif
	634
41e5ee54 SR	635	void enable_caches(void)
41e5ee54 SR	636	{
60b75324 SR	637	/* Avoid problem with e.g. neta ethernet driver */
	638	invalidate_dcache_all();
	639
ebe78903 SR	640	/*
	641	* Armada 375 still has some problems with d-cache enabled in the
	642	* ethernet driver (mvpp2). So lets keep the d-cache disabled
	643	* until this is solved.
	644	*/
117ef655	645	if (!IS_ENABLED(CONFIG_ARMADA_375)) {
ebe78903 SR	646	/* Enable D-cache. I-cache is already enabled in start.S */
	647	dcache_enable();
	648	}
41e5ee54	649	}
3e5ce7ce SR	650
	651	void v7_outer_cache_enable(void)
	652	{
4f2333ba	653	struct pl310_regs *const pl310 =
65cc0e2a	654	(struct pl310_regs *)CFG_SYS_PL310_BASE;
4f2333ba T	655
	656	/* The L2 cache is already disabled at this point */
	657
	658	/*
	659	* For now L2 cache will be enabled only for Armada XP and Armada 38x.
	660	* It can be enabled also for other SoCs after testing that it works fine.
	661	*/
	662	if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X))
	663	return;
	664
3308933d	665	if (IS_ENABLED(CONFIG_ARMADA_XP)) {
3e5ce7ce SR	666	u32 u;
	667
	668	/*
	669	* For Aurora cache in no outer mode, enable via the CP15
	670	* coprocessor broadcasting of cache commands to L2.
	671	*/
	672	asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
	673	u \|= BIT(8); /* Set the FW bit */
	674	asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
	675
	676	isb();
3e5ce7ce	677	}
4f2333ba T	678
	679	/* Enable the L2 cache */
	680	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
3e5ce7ce	681	}
f0e8173a SR	682
	683	void v7_outer_cache_disable(void)
	684	{
	685	struct pl310_regs *const pl310 =
65cc0e2a	686	(struct pl310_regs *)CFG_SYS_PL310_BASE;
f0e8173a SR	687
	688	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	689	}