[thirdparty/u-boot.git] / arch / arm / mach-mvebu / dram.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 */

#include <config.h>
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>

#if defined(CONFIG_ARCH_MVEBU)
/* Use common XOR definitions for A3x and AXP */
#include "../../../drivers/ddr/marvell/axp/xor.h"
#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
#endif

DECLARE_GLOBAL_DATA_PTR;

struct sdram_bank {
	u32	win_bar;
	u32	win_sz;
};

struct sdram_addr_dec {
	struct sdram_bank sdram_bank[4];
};

#define REG_CPUCS_WIN_ENABLE		(1 << 0)
#define REG_CPUCS_WIN_WR_PROTECT	(1 << 1)
#define REG_CPUCS_WIN_WIN0_CS(x)	(((x) & 0x3) << 2)
#define REG_CPUCS_WIN_SIZE(x)		(((x) & 0xff) << 24)

#ifndef MVEBU_SDRAM_SIZE_MAX
#define MVEBU_SDRAM_SIZE_MAX		0xc0000000
#endif

#define SCRUB_MAGIC		0xbeefdead

#define SCRB_XOR_UNIT		0
#define SCRB_XOR_CHAN		1
#define SCRB_XOR_WIN		0

#define XEBARX_BASE_OFFS	16

/*
 * mvebu_sdram_bar - reads SDRAM Base Address Register
 */
u32 mvebu_sdram_bar(enum memory_bank bank)
{
	struct sdram_addr_dec *base =
		(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
	u32 result = 0;
	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);

	if ((!enable) || (bank > BANK3))
		return 0;

	result = readl(&base->sdram_bank[bank].win_bar);
	return result;
}

/*
 * mvebu_sdram_bs_set - writes SDRAM Bank size
 */
static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
{
	struct sdram_addr_dec *base =
		(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
	/* Read current register value */
	u32 reg = readl(&base->sdram_bank[bank].win_sz);

	/* Clear window size */
	reg &= ~REG_CPUCS_WIN_SIZE(0xFF);

	/* Set new window size */
	reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);

	writel(reg, &base->sdram_bank[bank].win_sz);
}

/*
 * mvebu_sdram_bs - reads SDRAM Bank size
 */
u32 mvebu_sdram_bs(enum memory_bank bank)
{
	struct sdram_addr_dec *base =
		(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
	u32 result = 0;
	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);

	if ((!enable) || (bank > BANK3))
		return 0;
	result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
	result += 0x01000000;
	return result;
}

void mvebu_sdram_size_adjust(enum memory_bank bank)
{
	u32 size;

	/* probe currently equipped RAM size */
	size = get_ram_size((void *)mvebu_sdram_bar(bank),
			    mvebu_sdram_bs(bank));

	/* adjust SDRAM window size accordingly */
	mvebu_sdram_bs_set(bank, size);
}

#if defined(CONFIG_ARCH_MVEBU)
static u32 xor_ctrl_save;
static u32 xor_base_save;
static u32 xor_mask_save;

static void mv_xor_init2(u32 cs)
{
	u32 reg, base, size, base2;
	u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };

	xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
						     SCRB_XOR_CHAN));
	xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
						   SCRB_XOR_WIN));
	xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
						   SCRB_XOR_WIN));

	/* Enable Window x for each CS */
	reg = 0x1;
	reg |= (0x3 << 16);
	reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);

	base = 0;
	size = mvebu_sdram_bs(cs) - 1;
	if (size) {
		base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
			bank_attr[cs];
		reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
			  base2);

		base += size + 1;
		size = (size / (64 << 10)) << 16;
		/* Window x - size - 256 MB */
		reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
	}

	mv_xor_hal_init(0);

	return;
}

static void mv_xor_finish2(void)
{
	reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
		  xor_ctrl_save);
	reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
		  xor_base_save);
	reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
		  xor_mask_save);
}

static void dram_ecc_scrubbing(void)
{
	int cs;
	u32 size, temp;
	u32 total_mem = 0;
	u64 total;
	u32 start_addr;

	/*
	 * The DDR training code from the bin_hdr / SPL already
	 * scrubbed the DDR till 0x1000000. And the main U-Boot
	 * is loaded to an address < 0x1000000. So we need to
	 * skip this range to not re-scrub this area again.
	 */
	temp = reg_read(REG_SDRAM_CONFIG_ADDR);
	temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
	reg_write(REG_SDRAM_CONFIG_ADDR, temp);

	for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
		size = mvebu_sdram_bs(cs);
		if (size == 0)
			continue;

		total = (u64)size;
		total_mem += (u32)(total / (1 << 30));
		start_addr = 0;
		mv_xor_init2(cs);

		/* Skip first 16 MiB */
		if (0 == cs) {
			start_addr = 0x1000000;
			size -= start_addr;
		}

		mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
				SCRUB_MAGIC, SCRUB_MAGIC);

		/* Wait for previous transfer completion */
		while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
			;

		mv_xor_finish2();
	}

	temp = reg_read(REG_SDRAM_CONFIG_ADDR);
	temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
	reg_write(REG_SDRAM_CONFIG_ADDR, temp);
}

static int ecc_enabled(void)
{
	if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
		return 1;

	return 0;
}

/* Return the width of the DRAM bus. */
static int bus_width(void)
{
	int full_width = 0;

	if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
		full_width = 1;

#ifdef CONFIG_ARMADA_XP
	return full_width ? 64 : 32;
#else
	return full_width ? 32 : 16;
#endif
}

static int cycle_mode(void)
{
	int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);

	return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
}

#else
static void dram_ecc_scrubbing(void)
{
}

static int ecc_enabled(void)
{
	return 0;
}
#endif

int dram_init(void)
{
	u64 size = 0;
	int i;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		/*
		 * It is assumed that all memory banks are consecutive
		 * and without gaps.
		 * If the gap is found, ram_size will be reported for
		 * consecutive memory only
		 */
		if (mvebu_sdram_bar(i) != size)
			break;

		/*
		 * Don't report more than 3GiB of SDRAM, otherwise there is no
		 * address space left for the internal registers etc.
		 */
		size += mvebu_sdram_bs(i);
		if (size > MVEBU_SDRAM_SIZE_MAX)
			size = MVEBU_SDRAM_SIZE_MAX;
	}

	if (ecc_enabled())
		dram_ecc_scrubbing();

	gd->ram_size = size;

	return 0;
}

/*
 * If this function is not defined here,
 * board.c alters dram bank zero configuration defined above.
 */
int dram_init_banksize(void)
{
	u64 size = 0;
	int i;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
		gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);

		/* Clip the banksize to 1GiB if it exceeds the max size */
		size += gd->bd->bi_dram[i].size;
		if (size > MVEBU_SDRAM_SIZE_MAX)
			mvebu_sdram_bs_set(i, 0x40000000);
	}

	return 0;
}

#if defined(CONFIG_ARCH_MVEBU)
void board_add_ram_info(int use_default)
{
	struct sar_freq_modes sar_freq;
	int mode;
	int width;

	get_sar_freq(&sar_freq);
	printf(" (%d MHz, ", sar_freq.d_clk);

	width = bus_width();
	if (width)
		printf("%d-bit, ", width);

	mode = cycle_mode();
	/* Mode 0 = Single cycle
	 * Mode 1 = Two cycles   (2T)
	 * Mode 2 = Three cycles (3T)
	 */
	if (mode == 1)
		printf("2T, ");
	if (mode == 2)
		printf("3T, ");

	if (ecc_enabled())
		printf("ECC");
	else
		printf("ECC not");
	printf(" enabled)");
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4efb77d4 PW	2	/*
	3	* (C) Copyright 2009
	4	* Marvell Semiconductor <www.marvell.com>
	5	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
4efb77d4 PW	6	*/
	7
	8	#include <config.h>
d678a59d	9	#include <common.h>
9b4a205f	10	#include <init.h>
401d1c4f	11	#include <asm/global_data.h>
a7efd719 LW	12	#include <asm/io.h>
a7efd719 LW	13	#include <asm/arch/cpu.h>
3dc23f78	14	#include <asm/arch/soc.h>
4efb77d4	15
81e33f4b SR	16	#if defined(CONFIG_ARCH_MVEBU)
81e33f4b SR	17	/* Use common XOR definitions for A3x and AXP */
0ceb2dae SR	18	#include "../../../drivers/ddr/marvell/axp/xor.h"
0ceb2dae SR	19	#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
8a83c65f SR	20	#endif
8a83c65f SR	21
beeb2589 PW	22	DECLARE_GLOBAL_DATA_PTR;
beeb2589 PW	23
96c5f081	24	struct sdram_bank {
cf37c5d9 HB	25	u32 win_bar;
	26	u32 win_sz;
	27	};
	28
96c5f081 SR	29	struct sdram_addr_dec {
96c5f081 SR	30	struct sdram_bank sdram_bank[4];
cf37c5d9 HB	31	};
cf37c5d9 HB	32
96c5f081 SR	33	#define REG_CPUCS_WIN_ENABLE (1 << 0)
	34	#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
	35	#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
	36	#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
45515165	37
a8483505 SR	38	#ifndef MVEBU_SDRAM_SIZE_MAX
	39	#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
	40	#endif
a8b57a90	41
0ceb2dae SR	42	#define SCRUB_MAGIC 0xbeefdead
	43
	44	#define SCRB_XOR_UNIT 0
	45	#define SCRB_XOR_CHAN 1
	46	#define SCRB_XOR_WIN 0
	47
	48	#define XEBARX_BASE_OFFS 16
	49
4efb77d4	50	/*
96c5f081	51	* mvebu_sdram_bar - reads SDRAM Base Address Register
4efb77d4	52	*/
96c5f081	53	u32 mvebu_sdram_bar(enum memory_bank bank)
4efb77d4	54	{
96c5f081 SR	55	struct sdram_addr_dec *base =
96c5f081 SR	56	(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
4efb77d4	57	u32 result = 0;
cf37c5d9	58	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
4efb77d4 PW	59
	60	if ((!enable) \|\| (bank > BANK3))
	61	return 0;
	62
cf37c5d9	63	result = readl(&base->sdram_bank[bank].win_bar);
4efb77d4 PW	64	return result;
	65	}
	66
45515165	67	/*
96c5f081	68	* mvebu_sdram_bs_set - writes SDRAM Bank size
45515165	69	*/
96c5f081	70	static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
45515165	71	{
96c5f081 SR	72	struct sdram_addr_dec *base =
96c5f081 SR	73	(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
45515165 GF	74	/* Read current register value */
	75	u32 reg = readl(&base->sdram_bank[bank].win_sz);
	76
	77	/* Clear window size */
96c5f081	78	reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
45515165 GF	79
45515165 GF	80	/* Set new window size */
96c5f081	81	reg \|= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
45515165 GF	82
	83	writel(reg, &base->sdram_bank[bank].win_sz);
	84	}
	85
4efb77d4	86	/*
96c5f081	87	* mvebu_sdram_bs - reads SDRAM Bank size
4efb77d4	88	*/
96c5f081	89	u32 mvebu_sdram_bs(enum memory_bank bank)
4efb77d4	90	{
96c5f081 SR	91	struct sdram_addr_dec *base =
96c5f081 SR	92	(struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
4efb77d4	93	u32 result = 0;
cf37c5d9	94	u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
4efb77d4 PW	95
	96	if ((!enable) \|\| (bank > BANK3))
	97	return 0;
cf37c5d9	98	result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
4efb77d4 PW	99	result += 0x01000000;
	100	return result;
	101	}
beeb2589	102
96c5f081	103	void mvebu_sdram_size_adjust(enum memory_bank bank)
b3168f4b GF	104	{
	105	u32 size;
	106
	107	/* probe currently equipped RAM size */
96c5f081 SR	108	size = get_ram_size((void *)mvebu_sdram_bar(bank),
96c5f081 SR	109	mvebu_sdram_bs(bank));
b3168f4b GF	110
b3168f4b GF	111	/* adjust SDRAM window size accordingly */
96c5f081	112	mvebu_sdram_bs_set(bank, size);
b3168f4b GF	113	}
b3168f4b GF	114
81e33f4b	115	#if defined(CONFIG_ARCH_MVEBU)
0ceb2dae SR	116	static u32 xor_ctrl_save;
	117	static u32 xor_base_save;
	118	static u32 xor_mask_save;
	119
	120	static void mv_xor_init2(u32 cs)
	121	{
	122	u32 reg, base, size, base2;
	123	u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
	124
	125	xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
	126	SCRB_XOR_CHAN));
	127	xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
	128	SCRB_XOR_WIN));
	129	xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
	130	SCRB_XOR_WIN));
	131
	132	/* Enable Window x for each CS */
	133	reg = 0x1;
	134	reg \|= (0x3 << 16);
	135	reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
	136
	137	base = 0;
	138	size = mvebu_sdram_bs(cs) - 1;
	139	if (size) {
	140	base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) \|
	141	bank_attr[cs];
	142	reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
	143	base2);
	144
	145	base += size + 1;
	146	size = (size / (64 << 10)) << 16;
	147	/* Window x - size - 256 MB */
	148	reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
	149	}
	150
	151	mv_xor_hal_init(0);
	152
	153	return;
	154	}
	155
	156	static void mv_xor_finish2(void)
	157	{
	158	reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
	159	xor_ctrl_save);
	160	reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
	161	xor_base_save);
	162	reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
	163	xor_mask_save);
	164	}
	165
	166	static void dram_ecc_scrubbing(void)
	167	{
	168	int cs;
	169	u32 size, temp;
	170	u32 total_mem = 0;
	171	u64 total;
	172	u32 start_addr;
	173
	174	/*
	175	* The DDR training code from the bin_hdr / SPL already
	176	* scrubbed the DDR till 0x1000000. And the main U-Boot
	177	* is loaded to an address < 0x1000000. So we need to
	178	* skip this range to not re-scrub this area again.
	179	*/
180	temp = reg_read(REG_SDRAM_CONFIG_ADDR);
181	temp \|= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
182	reg_write(REG_SDRAM_CONFIG_ADDR, temp);
183
184	for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
c3ab2744	185	size = mvebu_sdram_bs(cs);
0ceb2dae SR	186	if (size == 0)
	187	continue;
	188
c3ab2744	189	total = (u64)size;
0ceb2dae SR	190	total_mem += (u32)(total / (1 << 30));
	191	start_addr = 0;
	192	mv_xor_init2(cs);
	193
	194	/* Skip first 16 MiB */
	195	if (0 == cs) {
	196	start_addr = 0x1000000;
	197	size -= start_addr;
	198	}
	199
c3ab2744	200	mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
0ceb2dae SR	201	SCRUB_MAGIC, SCRUB_MAGIC);
	202
	203	/* Wait for previous transfer completion */
	204	while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
	205	;
	206
	207	mv_xor_finish2();
	208	}
	209
	210	temp = reg_read(REG_SDRAM_CONFIG_ADDR);
	211	temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
	212	reg_write(REG_SDRAM_CONFIG_ADDR, temp);
	213	}
	214
	215	static int ecc_enabled(void)
	216	{
	217	if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
	218	return 1;
	219
	220	return 0;
	221	}
631407c5	222
3308933d	223	/* Return the width of the DRAM bus. */
631407c5 JS	224	static int bus_width(void)
	225	{
	226	int full_width = 0;
	227
	228	if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
	229	full_width = 1;
	230
3308933d T	231	#ifdef CONFIG_ARMADA_XP
	232	return full_width ? 64 : 32;
	233	#else
	234	return full_width ? 32 : 16;
	235	#endif
631407c5 JS	236	}
	237
	238	static int cycle_mode(void)
	239	{
	240	int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
	241
	242	return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
	243	}
	244
0ceb2dae SR	245	#else
	246	static void dram_ecc_scrubbing(void)
	247	{
	248	}
	249
	250	static int ecc_enabled(void)
	251	{
	252	return 0;
	253	}
	254	#endif
	255
beeb2589 PW	256	int dram_init(void)
beeb2589 PW	257	{
a8b57a90	258	u64 size = 0;
beeb2589 PW	259	int i;
beeb2589 PW	260
beeb2589	261	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
beeb2589 PW	262	/*
	263	* It is assumed that all memory banks are consecutive
	264	* and without gaps.
	265	* If the gap is found, ram_size will be reported for
	266	* consecutive memory only
	267	*/
a8b57a90	268	if (mvebu_sdram_bar(i) != size)
beeb2589 PW	269	break;
beeb2589 PW	270
d80cca29 SR	271	/*
	272	* Don't report more than 3GiB of SDRAM, otherwise there is no
	273	* address space left for the internal registers etc.
	274	*/
a8b57a90	275	size += mvebu_sdram_bs(i);
a8483505 SR	276	if (size > MVEBU_SDRAM_SIZE_MAX)
a8483505 SR	277	size = MVEBU_SDRAM_SIZE_MAX;
beeb2589	278	}
28e57108	279
0ceb2dae SR	280	if (ecc_enabled())
	281	dram_ecc_scrubbing();
	282
a8b57a90 SR	283	gd->ram_size = size;
a8b57a90 SR	284
beeb2589 PW	285	return 0;
	286	}
	287
	288	/*
	289	* If this function is not defined here,
	290	* board.c alters dram bank zero configuration defined above.
	291	*/
76b00aca	292	int dram_init_banksize(void)
beeb2589	293	{
a8b57a90 SR	294	u64 size = 0;
	295	int i;
	296
	297	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	298	gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
	299	gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
	300
	301	/* Clip the banksize to 1GiB if it exceeds the max size */
	302	size += gd->bd->bi_dram[i].size;
a8483505	303	if (size > MVEBU_SDRAM_SIZE_MAX)
a8b57a90 SR	304	mvebu_sdram_bs_set(i, 0x40000000);
a8b57a90 SR	305	}
76b00aca SG	306
76b00aca SG	307	return 0;
beeb2589	308	}
8a83c65f	309
81e33f4b	310	#if defined(CONFIG_ARCH_MVEBU)
8a83c65f SR	311	void board_add_ram_info(int use_default)
8a83c65f SR	312	{
d718bf2c	313	struct sar_freq_modes sar_freq;
631407c5 JS	314	int mode;
631407c5 JS	315	int width;
d718bf2c SR	316
	317	get_sar_freq(&sar_freq);
	318	printf(" (%d MHz, ", sar_freq.d_clk);
	319
631407c5 JS	320	width = bus_width();
	321	if (width)
	322	printf("%d-bit, ", width);
	323
	324	mode = cycle_mode();
	325	/* Mode 0 = Single cycle
	326	* Mode 1 = Two cycles (2T)
	327	* Mode 2 = Three cycles (3T)
	328	*/
	329	if (mode == 1)
	330	printf("2T, ");
	331	if (mode == 2)
	332	printf("3T, ");
	333
0ceb2dae	334	if (ecc_enabled())
d718bf2c	335	printf("ECC");
8a83c65f	336	else
d718bf2c	337	printf("ECC not");
8a83c65f SR	338	printf(" enabled)");
8a83c65f SR	339	}
d718bf2c	340	#endif