[people/ms/u-boot.git] / arch / arm / mach-mvebu / include / mach / cpu.h

/*
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _MVEBU_CPU_H
#define _MVEBU_CPU_H

#include <asm/system.h>

#ifndef __ASSEMBLY__

#define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
#define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)

enum memory_bank {
	BANK0,
	BANK1,
	BANK2,
	BANK3
};

enum cpu_winen {
	CPU_WIN_DISABLE,
	CPU_WIN_ENABLE
};

enum cpu_target {
	CPU_TARGET_DRAM = 0x0,
	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
	CPU_TARGET_ETH23 = 0x3,
	CPU_TARGET_PCIE02 = 0x4,
	CPU_TARGET_ETH01 = 0x7,
	CPU_TARGET_PCIE13 = 0x8,
	CPU_TARGET_SASRAM = 0x9,
	CPU_TARGET_NAND = 0xd,
};

enum cpu_attrib {
	CPU_ATTR_SASRAM = 0x01,
	CPU_ATTR_DRAM_CS0 = 0x0e,
	CPU_ATTR_DRAM_CS1 = 0x0d,
	CPU_ATTR_DRAM_CS2 = 0x0b,
	CPU_ATTR_DRAM_CS3 = 0x07,
	CPU_ATTR_NANDFLASH = 0x2f,
	CPU_ATTR_SPIFLASH = 0x1e,
	CPU_ATTR_BOOTROM = 0x1d,
	CPU_ATTR_PCIE_IO = 0xe0,
	CPU_ATTR_PCIE_MEM = 0xe8,
	CPU_ATTR_DEV_CS0 = 0x3e,
	CPU_ATTR_DEV_CS1 = 0x3d,
	CPU_ATTR_DEV_CS2 = 0x3b,
	CPU_ATTR_DEV_CS3 = 0x37,
};

enum {
	MVEBU_SOC_AXP,
	MVEBU_SOC_A38X,
	MVEBU_SOC_UNKNOWN,
};

/*
 * Default Device Address MAP BAR values
 */
#define MBUS_PCI_MEM_BASE	0xE8000000
#define MBUS_PCI_MEM_SIZE	(128 << 20)
#define MBUS_PCI_IO_BASE	0xF1100000
#define MBUS_PCI_IO_SIZE	(64 << 10)
#define MBUS_SPI_BASE		0xF4000000
#define MBUS_SPI_SIZE		(8 << 20)
#define MBUS_BOOTROM_BASE	0xF8000000
#define MBUS_BOOTROM_SIZE	(8 << 20)

struct mbus_win {
	u32 base;
	u32 size;
	u8 target;
	u8 attr;
};

/*
 * System registers
 * Ref: Datasheet sec:A.28
 */
struct mvebu_system_registers {
	u8 pad1[0x60];
	u32 rstoutn_mask; /* 0x60 */
	u32 sys_soft_rst; /* 0x64 */
};

/*
 * GPIO Registers
 * Ref: Datasheet sec:A.19
 */
struct kwgpio_registers {
	u32 dout;
	u32 oe;
	u32 blink_en;
	u32 din_pol;
	u32 din;
	u32 irq_cause;
	u32 irq_mask;
	u32 irq_level;
};

struct sar_freq_modes {
	u8 val;
	u8 ffc;		/* Fabric Frequency Configuration */
	u32 p_clk;
	u32 nb_clk;
	u32 d_clk;
};

/* Needed for dynamic (board-specific) mbus configuration */
extern struct mvebu_mbus_state mbus_state;

/*
 * functions
 */
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
int mvebu_soc_family(void);
u32 mvebu_get_nand_clock(void);

void return_to_bootrom(void);

int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);

void get_sar_freq(struct sar_freq_modes *sar_freq);

/*
 * Highspeed SERDES PHY config init, ported from bin_hdr
 * to mainline U-Boot
 */
int serdes_phy_config(void);

/*
 * DDR3 init / training code ported from Marvell bin_hdr. Now
 * available in mainline U-Boot in:
 * drivers/ddr/marvell
 */
int ddr3_init(void);

struct mvebu_lcd_info {
	u32 fb_base;
	int x_res;
	int y_res;
	int x_fp;		/* frontporch */
	int y_fp;
	int x_bp;		/* backporch */
	int y_bp;
};

int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);

#endif /* __ASSEMBLY__ */
#endif /* _MVEBU_CPU_H */
Commit	Line	Data
41e5ee54 SR	1	/*
	2	* (C) Copyright 2009
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
250eea74 SR	9	#ifndef _MVEBU_CPU_H
250eea74 SR	10	#define _MVEBU_CPU_H
41e5ee54 SR	11
	12	#include <asm/system.h>
	13
	14	#ifndef __ASSEMBLY__
	15
	16	#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
	17	#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
	18
	19	enum memory_bank {
	20	BANK0,
	21	BANK1,
	22	BANK2,
	23	BANK3
	24	};
	25
	26	enum cpu_winen {
	27	CPU_WIN_DISABLE,
	28	CPU_WIN_ENABLE
	29	};
	30
	31	enum cpu_target {
	32	CPU_TARGET_DRAM = 0x0,
	33	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
	34	CPU_TARGET_ETH23 = 0x3,
	35	CPU_TARGET_PCIE02 = 0x4,
	36	CPU_TARGET_ETH01 = 0x7,
	37	CPU_TARGET_PCIE13 = 0x8,
	38	CPU_TARGET_SASRAM = 0x9,
	39	CPU_TARGET_NAND = 0xd,
	40	};
	41
	42	enum cpu_attrib {
	43	CPU_ATTR_SASRAM = 0x01,
	44	CPU_ATTR_DRAM_CS0 = 0x0e,
	45	CPU_ATTR_DRAM_CS1 = 0x0d,
	46	CPU_ATTR_DRAM_CS2 = 0x0b,
	47	CPU_ATTR_DRAM_CS3 = 0x07,
	48	CPU_ATTR_NANDFLASH = 0x2f,
	49	CPU_ATTR_SPIFLASH = 0x1e,
	50	CPU_ATTR_BOOTROM = 0x1d,
	51	CPU_ATTR_PCIE_IO = 0xe0,
	52	CPU_ATTR_PCIE_MEM = 0xe8,
	53	CPU_ATTR_DEV_CS0 = 0x3e,
	54	CPU_ATTR_DEV_CS1 = 0x3d,
	55	CPU_ATTR_DEV_CS2 = 0x3b,
	56	CPU_ATTR_DEV_CS3 = 0x37,
	57	};
	58
9c6d3b7b SR	59	enum {
	60	MVEBU_SOC_AXP,
	61	MVEBU_SOC_A38X,
	62	MVEBU_SOC_UNKNOWN,
	63	};
	64
41e5ee54 SR	65	/*
	66	* Default Device Address MAP BAR values
	67	*/
8ed20d65 SR	68	#define MBUS_PCI_MEM_BASE 0xE8000000
	69	#define MBUS_PCI_MEM_SIZE (128 << 20)
	70	#define MBUS_PCI_IO_BASE 0xF1100000
	71	#define MBUS_PCI_IO_SIZE (64 << 10)
	72	#define MBUS_SPI_BASE 0xF4000000
	73	#define MBUS_SPI_SIZE (8 << 20)
	74	#define MBUS_BOOTROM_BASE 0xF8000000
	75	#define MBUS_BOOTROM_SIZE (8 << 20)
41e5ee54 SR	76
	77	struct mbus_win {
	78	u32 base;
	79	u32 size;
	80	u8 target;
	81	u8 attr;
	82	};
	83
	84	/*
	85	* System registers
	86	* Ref: Datasheet sec:A.28
	87	*/
	88	struct mvebu_system_registers {
	89	u8 pad1[0x60];
	90	u32 rstoutn_mask; /* 0x60 */
	91	u32 sys_soft_rst; /* 0x64 */
	92	};
	93
	94	/*
	95	* GPIO Registers
	96	* Ref: Datasheet sec:A.19
	97	*/
	98	struct kwgpio_registers {
	99	u32 dout;
	100	u32 oe;
	101	u32 blink_en;
	102	u32 din_pol;
	103	u32 din;
	104	u32 irq_cause;
	105	u32 irq_mask;
	106	u32 irq_level;
	107	};
	108
d718bf2c SR	109	struct sar_freq_modes {
	110	u8 val;
	111	u8 ffc; /* Fabric Frequency Configuration */
	112	u32 p_clk;
	113	u32 nb_clk;
	114	u32 d_clk;
	115	};
	116
e7778ec1 SR	117	/* Needed for dynamic (board-specific) mbus configuration */
	118	extern struct mvebu_mbus_state mbus_state;
	119
41e5ee54 SR	120	/*
	121	* functions
	122	*/
	123	unsigned int mvebu_sdram_bar(enum memory_bank bank);
	124	unsigned int mvebu_sdram_bs(enum memory_bank bank);
	125	void mvebu_sdram_size_adjust(enum memory_bank bank);
	126	int mvebu_mbus_probe(struct mbus_win windows[], int count);
9c6d3b7b	127	int mvebu_soc_family(void);
2a0b7dc3	128	u32 mvebu_get_nand_clock(void);
b0f80b91	129
944c7a31 SR	130	void return_to_bootrom(void);
944c7a31 SR	131
7f1adcd7 SR	132	int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
7f1adcd7 SR	133
d718bf2c SR	134	void get_sar_freq(struct sar_freq_modes *sar_freq);
d718bf2c SR	135
b0f80b91 SR	136	/*
	137	* Highspeed SERDES PHY config init, ported from bin_hdr
	138	* to mainline U-Boot
	139	*/
	140	int serdes_phy_config(void);
	141
	142	/*
	143	* DDR3 init / training code ported from Marvell bin_hdr. Now
	144	* available in mainline U-Boot in:
ff9112df	145	* drivers/ddr/marvell
b0f80b91 SR	146	*/
b0f80b91 SR	147	int ddr3_init(void);
913d1be2 SR	148
	149	struct mvebu_lcd_info {
	150	u32 fb_base;
	151	int x_res;
	152	int y_res;
	153	int x_fp; /* frontporch */
	154	int y_fp;
	155	int x_bp; /* backporch */
	156	int y_bp;
	157	};
	158
	159	int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
	160
41e5ee54	161	#endif /* __ASSEMBLY__ */
250eea74	162	#endif /* _MVEBU_CPU_H */