[thirdparty/u-boot.git] / arch / arm / mach-mvebu / serdes / axp / high_speed_env_spec.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) Marvell International Ltd. and its affiliates
 */

#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>

#include "high_speed_env_spec.h"

MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
	/* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
	{
		/* PEX: Change of Slew Rate port0   */
		SERDES_UNIT_PEX, 0x0,
		(0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
	}, {
		/* PEX: Change PLL BW port0                   */
		SERDES_UNIT_PEX, 0x0,
		(0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
	}, {
		/* SATA: Slew rate change port 0  */
		SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
	}, {
		/* SATA: Slew rate change port 0  */
		SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
	}, {
		/* SATA: Slew rate change port 0  */
		SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
	}, {
		/* SATA: Slew rate change port 0  */
		SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
	}, {
		/* SGMII: FFE setting Port0         */
		SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
	}, {
		/* SGMII: SELMUP and SELMUF Port0   */
		SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
	}, {
		/* SGMII: Amplitude new setting gen2 Port3 */
		SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
	}, {
		/* QSGMII: Amplitude and slew rate change  */
		SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
	}, {
		/* QSGMII: SELMUP and SELMUF               */
		SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
	}, {
		/* QSGMII: 0x72e18                         */
		SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
	}, {
		/* Null terminated */
		SERDES_UNIT_UNCONNECTED, 0, 0
	}
};

MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
	/* Z1B */
	{MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy},			/* Default */
	{MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy},			/* PEX module */
	/* Z1A */
	{MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
	 {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
	  PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
	{MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
	 {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0030, serdes_change_m_phy}	/* PEX module - Z1A */
};

MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
	/* A0 */
	{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
	{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
	{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
	{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
	 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
	{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
	{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
	 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
};

MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}, /* Default */
	{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x00f4, serdes_change_m_phy}, /* Switch module */
};

MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0010, serdes_change_m_phy}, /* CPU0 */
	{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0010, serdes_change_m_phy} /* CPU1-3 */
};

MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0010, serdes_change_m_phy}, /* CPU0 */
	{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0010, serdes_change_m_phy} /* CPU1-3 */
};

MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
	{MV_PEX_END_POINT, 0x22321111, 0x00000000,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0010, serdes_change_m_phy}	/* Default */
};

MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
	{MV_PEX_END_POINT, 0x23321111, 0x00000000,
	 {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0010, serdes_change_m_phy}	/* Default */
};

MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
	 {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
	 0x0000, serdes_change_m_phy}	/* No PEX in FPGA */
};

MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
	 {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
	 0x0030, serdes_change_m_phy}	/* Default */
};

/*
 * ARMADA-XP CUSTOMER BOARD
 */
MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x00000030, serdes_change_m_phy}, /* Default */
	{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x00000030, serdes_change_m_phy}, /* Switch module */
};

MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
	{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
	 {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	 0x0030, serdes_change_m_phy}	/* Default */
};

MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
	db88f78xx0_serdes_cfg,
	rd78460_serdes_cfg,
	db78X60pcac_serdes_cfg,
	fpga88f78xx0_serdes_cfg,
	db88f78xx0rev2_serdes_cfg,
	rd78460nas_serdes_cfg,
	db78X60amc_serdes_cfg,
	db78X60pcacrev2_serdes_cfg,
	rd78460server_rev2_serdes_cfg,
	rd78460AXP_GP_serdes_cfg,
	rd78460customer_serdes_cfg
};

u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
2e19cc31 SR	2	/*
2e19cc31 SR	3	* Copyright (C) Marvell International Ltd. and its affiliates
2e19cc31 SR	4	*/
2e19cc31 SR	5
d678a59d	6	#include <common.h>
2e19cc31 SR	7	#include <spl.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/cpu.h>
	10	#include <asm/arch/soc.h>
	11
	12	#include "high_speed_env_spec.h"
	13
	14	MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
	15	/* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
	16	{
	17	/* PEX: Change of Slew Rate port0 */
	18	SERDES_UNIT_PEX, 0x0,
	19	(0x0F << 16) \| 0x2a21, 0x0, (0x0F << 16) \| 0x2a21
	20	}, {
	21	/* PEX: Change PLL BW port0 */
	22	SERDES_UNIT_PEX, 0x0,
	23	(0x4F << 16) \| 0x6219, 0x0, (0x4F << 16) \| 0x6219
	24	}, {
	25	/* SATA: Slew rate change port 0 */
	26	SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
	27	}, {
	28	/* SATA: Slew rate change port 0 */
	29	SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
	30	}, {
	31	/* SATA: Slew rate change port 0 */
	32	SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
	33	}, {
	34	/* SATA: Slew rate change port 0 */
	35	SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
	36	}, {
	37	/* SGMII: FFE setting Port0 */
	38	SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
	39	}, {
	40	/* SGMII: SELMUP and SELMUF Port0 */
	41	SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
	42	}, {
	43	/* SGMII: Amplitude new setting gen2 Port3 */
	44	SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
	45	}, {
	46	/* QSGMII: Amplitude and slew rate change */
	47	SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
	48	}, {
	49	/* QSGMII: SELMUP and SELMUF */
	50	SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
	51	}, {
	52	/* QSGMII: 0x72e18 */
	53	SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
	54	}, {
	55	/* Null terminated */
	56	SERDES_UNIT_UNCONNECTED, 0, 0
	57	}
	58	};
	59
	60	MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
	61	/* Z1B */
	62	{MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
	63	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	64	0x0030, serdes_change_m_phy}, /* Default */
	65	{MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
	66	{PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
	67	0x0030, serdes_change_m_phy}, /* PEX module */
	68	/* Z1A */
	69	{MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
	70	{PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
71	PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
72	{MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
73	{PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
74	0x0030, serdes_change_m_phy} /* PEX module - Z1A */
75	};
76
77	MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
78	/* A0 */
79	{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
80	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
81	0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
82	{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
83	{PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
84	0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
85	{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
86	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
87	0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
88	{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
89	{PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
90	0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
91	{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
92	{PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
93	0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
94	{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
95	{PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
96	0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
97	};
98
99	MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
100	{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
101	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
102	0x0030, serdes_change_m_phy}, /* Default */
103	{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
104	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
105	0x00f4, serdes_change_m_phy}, /* Switch module */
106	};
107
108	MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
109	{MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
110	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
111	0x0010, serdes_change_m_phy}, /* CPU0 */
112	{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
113	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
114	0x0010, serdes_change_m_phy} /* CPU1-3 */
115	};
116
117	MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
118	{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
119	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
120	0x0010, serdes_change_m_phy}, /* CPU0 */
121	{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
122	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
123	0x0010, serdes_change_m_phy} /* CPU1-3 */
124	};
125
126	MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
127	{MV_PEX_END_POINT, 0x22321111, 0x00000000,
128	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
129	0x0010, serdes_change_m_phy} /* Default */
130	};
131
132	MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
133	{MV_PEX_END_POINT, 0x23321111, 0x00000000,
134	{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
135	0x0010, serdes_change_m_phy} /* Default */
136	};
137
138	MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
139	{MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
140	{PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
141	0x0000, serdes_change_m_phy} /* No PEX in FPGA */
142	};
143
144	MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
145	{MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
146	{PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
147	0x0030, serdes_change_m_phy} /* Default */
148	};
149
150	/*
151	* ARMADA-XP CUSTOMER BOARD
152	*/
153	MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
154	{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
155	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
156	0x00000030, serdes_change_m_phy}, /* Default */
157	{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
158	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
159	0x00000030, serdes_change_m_phy}, /* Switch module */
160	};
161
162	MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
163	{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
164	{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
165	0x0030, serdes_change_m_phy} /* Default */
166	};
167
168	MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
169	db88f78xx0_serdes_cfg,
170	rd78460_serdes_cfg,
171	db78X60pcac_serdes_cfg,
172	fpga88f78xx0_serdes_cfg,
173	db88f78xx0rev2_serdes_cfg,
174	rd78460nas_serdes_cfg,
175	db78X60amc_serdes_cfg,
176	db78X60pcacrev2_serdes_cfg,
177	rd78460server_rev2_serdes_cfg,
178	rd78460AXP_GP_serdes_cfg,
179	rd78460customer_serdes_cfg
180	};
181
182	u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
183	u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };