[thirdparty/u-boot.git] / arch / arm / mach-mvebu / system-controller.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
 * Copyright (C) 2024 Marek Behún <kabel@kernel.org>
 */

#include <common.h>
#include <dm.h>
#include <dm/lists.h>
#include <regmap.h>
#include <reset-uclass.h>
#include <syscon.h>
#include <sysreset.h>
#include <asm/io.h>

#define MVEBU_SOC_CONTROL_1_REG		0x4

#if defined(CONFIG_ARMADA_375)
# define MVEBU_RSTOUTN_MASK_REG		0x54
# define MVEBU_SYS_SOFT_RST_REG		0x58
#else
# define MVEBU_RSTOUTN_MASK_REG		0x60
# define MVEBU_SYS_SOFT_RST_REG		0x64
#endif

#define MVEBU_GLOBAL_SOFT_RST_BIT	BIT(0)

#define MVEBU_PCIE_ID			0

#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)

static int mvebu_reset_of_xlate(struct reset_ctl *rst,
				struct ofnode_phandle_args *args)
{
	if (args->args_count < 2)
		return -EINVAL;

	rst->id = args->args[0];
	rst->data = args->args[1];

	/* Currently only PCIe is implemented */
	if (rst->id != MVEBU_PCIE_ID)
		return -EINVAL;

	/* Four PCIe enable bits are shared across more PCIe links */
	if (!(rst->data >= 0 && rst->data <= 3))
		return -EINVAL;

	return 0;
}

static int mvebu_reset_request(struct reset_ctl *rst)
{
	return 0;
}

static int mvebu_reset_free(struct reset_ctl *rst)
{
	return 0;
}

static int mvebu_reset_assert(struct reset_ctl *rst)
{
	struct regmap *regmap = syscon_get_regmap(rst->dev->parent);

	return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
				  BIT(rst->data), 0);
}

static int mvebu_reset_deassert(struct reset_ctl *rst)
{
	struct regmap *regmap = syscon_get_regmap(rst->dev->parent);

	return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
				  BIT(rst->data), BIT(rst->data));
}

static int mvebu_reset_status(struct reset_ctl *rst)
{
	struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
	uint val;
	int ret;

	ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val);
	if (ret < 0)
		return ret;

	return !(val & BIT(rst->data));
}

static const struct reset_ops mvebu_reset_ops = {
	.of_xlate = mvebu_reset_of_xlate,
	.request = mvebu_reset_request,
	.rfree = mvebu_reset_free,
	.rst_assert = mvebu_reset_assert,
	.rst_deassert = mvebu_reset_deassert,
	.rst_status = mvebu_reset_status,
};

U_BOOT_DRIVER(mvebu_reset) = {
	.name = "mvebu-reset",
	.id = UCLASS_RESET,
	.ops = &mvebu_reset_ops,
};

#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */

#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)

static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
	struct regmap *regmap = syscon_get_regmap(dev->parent);
	uint bit;

	if (type != SYSRESET_COLD)
		return -EPROTONOSUPPORT;

	bit = MVEBU_GLOBAL_SOFT_RST_BIT;

	regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit);
	regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit);

	/* Loop while waiting for the reset */
	while (1)
		;

	return 0;
}

static struct sysreset_ops mvebu_sysreset_ops = {
	.request = mvebu_sysreset_request,
};

U_BOOT_DRIVER(mvebu_sysreset) = {
	.name = "mvebu-sysreset",
	.id = UCLASS_SYSRESET,
	.ops = &mvebu_sysreset_ops,
};

#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */

static int mvebu_syscon_bind(struct udevice *dev)
{
	int ret = 0;

	/* bind also mvebu-reset, with the same ofnode */
	if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) {
		ret = device_bind_driver_to_node(dev, "mvebu-reset",
						 "mvebu-reset", dev_ofnode(dev),
						 NULL);
		if (ret < 0)
			return ret;
	}

	/* bind also mvebu-sysreset, with the same ofnode */
	if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) {
		ret = device_bind_driver_to_node(dev, "mvebu-sysreset",
						 "mvebu-sysreset",
						 dev_ofnode(dev), NULL);
		if (ret < 0)
			return ret;
	}

	return ret;
}

static const struct udevice_id mvebu_syscon_of_match[] = {
	{ .compatible = "marvell,armada-370-xp-system-controller" },
	{ .compatible = "marvell,armada-375-system-controller" },
	{ .compatible = "marvell,armada-380-system-controller" },
	{ .compatible = "marvell,armada-390-system-controller" },
	{ },
};

U_BOOT_DRIVER(mvebu_syscon) = {
	.name = "mvebu-system-controller",
	.id = UCLASS_SYSCON,
	.of_match = mvebu_syscon_of_match,
	.bind = mvebu_syscon_bind,
};
Commit	Line	Data
35e29e89	1	// SPDX-License-Identifier: GPL-2.0+
ab900a6a MB	2	/*
	3	* Copyright (C) 2021 Pali Rohár <pali@kernel.org>
	4	* Copyright (C) 2024 Marek Behún <kabel@kernel.org>
	5	*/
35e29e89	6
d678a59d	7	#include <common.h>
35e29e89	8	#include <dm.h>
ab900a6a MB	9	#include <dm/lists.h>
ab900a6a MB	10	#include <regmap.h>
35e29e89	11	#include <reset-uclass.h>
ab900a6a	12	#include <syscon.h>
0c350a67	13	#include <sysreset.h>
35e29e89 T	14	#include <asm/io.h>
35e29e89 T	15
0c350a67	16	#define MVEBU_SOC_CONTROL_1_REG 0x4
35e29e89	17
0c350a67 MB	18	#if defined(CONFIG_ARMADA_375)
	19	# define MVEBU_RSTOUTN_MASK_REG 0x54
	20	# define MVEBU_SYS_SOFT_RST_REG 0x58
	21	#else
	22	# define MVEBU_RSTOUTN_MASK_REG 0x60
	23	# define MVEBU_SYS_SOFT_RST_REG 0x64
	24	#endif
	25
	26	#define MVEBU_GLOBAL_SOFT_RST_BIT BIT(0)
	27
	28	#define MVEBU_PCIE_ID 0
	29
	30	#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)
35e29e89	31
35e29e89 T	32	static int mvebu_reset_of_xlate(struct reset_ctl *rst,
	33	struct ofnode_phandle_args *args)
	34	{
	35	if (args->args_count < 2)
	36	return -EINVAL;
	37
	38	rst->id = args->args[0];
	39	rst->data = args->args[1];
	40
	41	/* Currently only PCIe is implemented */
	42	if (rst->id != MVEBU_PCIE_ID)
	43	return -EINVAL;
	44
	45	/* Four PCIe enable bits are shared across more PCIe links */
	46	if (!(rst->data >= 0 && rst->data <= 3))
	47	return -EINVAL;
	48
	49	return 0;
	50	}
	51
	52	static int mvebu_reset_request(struct reset_ctl *rst)
	53	{
	54	return 0;
	55	}
	56
	57	static int mvebu_reset_free(struct reset_ctl *rst)
	58	{
	59	return 0;
	60	}
	61
	62	static int mvebu_reset_assert(struct reset_ctl *rst)
	63	{
ab900a6a	64	struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
35e29e89	65
ab900a6a MB	66	return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
ab900a6a MB	67	BIT(rst->data), 0);
35e29e89 T	68	}
	69
	70	static int mvebu_reset_deassert(struct reset_ctl *rst)
	71	{
ab900a6a	72	struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
35e29e89	73
ab900a6a MB	74	return regmap_update_bits(regmap, MVEBU_SOC_CONTROL_1_REG,
ab900a6a MB	75	BIT(rst->data), BIT(rst->data));
35e29e89 T	76	}
	77
	78	static int mvebu_reset_status(struct reset_ctl *rst)
	79	{
ab900a6a MB	80	struct regmap *regmap = syscon_get_regmap(rst->dev->parent);
	81	uint val;
	82	int ret;
35e29e89	83
ab900a6a MB	84	ret = regmap_read(regmap, MVEBU_SOC_CONTROL_1_REG, &val);
	85	if (ret < 0)
	86	return ret;
35e29e89	87
ab900a6a	88	return !(val & BIT(rst->data));
35e29e89 T	89	}
35e29e89 T	90
b120519d	91	static const struct reset_ops mvebu_reset_ops = {
35e29e89 T	92	.of_xlate = mvebu_reset_of_xlate,
	93	.request = mvebu_reset_request,
	94	.rfree = mvebu_reset_free,
	95	.rst_assert = mvebu_reset_assert,
	96	.rst_deassert = mvebu_reset_deassert,
	97	.rst_status = mvebu_reset_status,
	98	};
	99
	100	U_BOOT_DRIVER(mvebu_reset) = {
	101	.name = "mvebu-reset",
	102	.id = UCLASS_RESET,
35e29e89 T	103	.ops = &mvebu_reset_ops,
35e29e89 T	104	};
ab900a6a	105
0c350a67 MB	106	#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET) */
	107
	108	#if IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
	109
	110	static int mvebu_sysreset_request(struct udevice *dev, enum sysreset_t type)
	111	{
	112	struct regmap *regmap = syscon_get_regmap(dev->parent);
	113	uint bit;
	114
	115	if (type != SYSRESET_COLD)
	116	return -EPROTONOSUPPORT;
	117
	118	bit = MVEBU_GLOBAL_SOFT_RST_BIT;
	119
	120	regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit);
	121	regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit);
	122
	123	/* Loop while waiting for the reset */
	124	while (1)
	125	;
	126
	127	return 0;
	128	}
	129
	130	static struct sysreset_ops mvebu_sysreset_ops = {
	131	.request = mvebu_sysreset_request,
	132	};
	133
	134	U_BOOT_DRIVER(mvebu_sysreset) = {
	135	.name = "mvebu-sysreset",
	136	.id = UCLASS_SYSRESET,
	137	.ops = &mvebu_sysreset_ops,
	138	};
	139
	140	#endif /* IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET) */
	141
ab900a6a MB	142	static int mvebu_syscon_bind(struct udevice *dev)
ab900a6a MB	143	{
0c350a67 MB	144	int ret = 0;
0c350a67 MB	145
ab900a6a	146	/* bind also mvebu-reset, with the same ofnode */
0c350a67 MB	147	if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_RESET)) {
	148	ret = device_bind_driver_to_node(dev, "mvebu-reset",
	149	"mvebu-reset", dev_ofnode(dev),
	150	NULL);
	151	if (ret < 0)
	152	return ret;
	153	}
	154
	155	/* bind also mvebu-sysreset, with the same ofnode */
	156	if (IS_ENABLED(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)) {
	157	ret = device_bind_driver_to_node(dev, "mvebu-sysreset",
	158	"mvebu-sysreset",
	159	dev_ofnode(dev), NULL);
	160	if (ret < 0)
	161	return ret;
	162	}
	163
	164	return ret;
ab900a6a MB	165	}
	166
	167	static const struct udevice_id mvebu_syscon_of_match[] = {
	168	{ .compatible = "marvell,armada-370-xp-system-controller" },
	169	{ .compatible = "marvell,armada-375-system-controller" },
	170	{ .compatible = "marvell,armada-380-system-controller" },
	171	{ .compatible = "marvell,armada-390-system-controller" },
	172	{ },
	173	};
	174
	175	U_BOOT_DRIVER(mvebu_syscon) = {
	176	.name = "mvebu-system-controller",
	177	.id = UCLASS_SYSCON,
	178	.of_match = mvebu_syscon_of_match,
	179	.bind = mvebu_syscon_bind,
	180	};