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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
a73c8b32 | 2 | /* |
a94a4071 | 3 | * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/ |
a73c8b32 | 4 | * Copyright (C) 2017, Grinn - http://grinn-global.com/ |
a73c8b32 MN |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
691d719d | 8 | #include <init.h> |
a73c8b32 MN |
9 | #include <asm/arch/clock.h> |
10 | #include <asm/arch/clk_synthesizer.h> | |
11 | #include <asm/arch/cpu.h> | |
12 | #include <asm/arch/ddr_defs.h> | |
13 | #include <asm/arch/hardware.h> | |
14 | #include <asm/arch/omap.h> | |
15 | #include <asm/arch/mem.h> | |
16 | #include <asm/arch/mux.h> | |
17 | #include <asm/arch/sys_proto.h> | |
18 | #include <asm/emif.h> | |
19 | #include <asm/io.h> | |
20 | #include <errno.h> | |
21 | #include <i2c.h> | |
22 | #include <power/tps65217.h> | |
23 | #include <spl.h> | |
24 | ||
a2ac2b96 | 25 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
a73c8b32 MN |
26 | |
27 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | |
28 | ||
29 | static struct module_pin_mux i2c0_pin_mux[] = { | |
30 | {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | | |
31 | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ | |
32 | {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | | |
33 | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ | |
34 | {-1}, | |
35 | }; | |
36 | ||
37 | static struct module_pin_mux nand_pin_mux[] = { | |
38 | {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ | |
39 | {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ | |
40 | {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ | |
41 | {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ | |
42 | {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ | |
43 | {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ | |
44 | {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ | |
45 | {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ | |
46 | {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ | |
47 | {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ | |
48 | {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ | |
49 | {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ | |
50 | {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ | |
51 | {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ | |
52 | {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ | |
53 | {-1}, | |
54 | }; | |
55 | ||
56 | static void enable_i2c0_pin_mux(void) | |
57 | { | |
58 | configure_module_pin_mux(i2c0_pin_mux); | |
59 | } | |
60 | ||
61 | void chilisom_enable_pin_mux(void) | |
62 | { | |
63 | /* chilisom pin mux */ | |
64 | configure_module_pin_mux(nand_pin_mux); | |
65 | } | |
66 | ||
67 | static const struct ddr_data ddr3_chilisom_data = { | |
68 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, | |
69 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, | |
70 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, | |
71 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, | |
72 | }; | |
73 | ||
74 | static const struct cmd_control ddr3_chilisom_cmd_ctrl_data = { | |
75 | .cmd0csratio = MT41K256M16HA125E_RATIO, | |
76 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
77 | ||
78 | .cmd1csratio = MT41K256M16HA125E_RATIO, | |
79 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
80 | ||
81 | .cmd2csratio = MT41K256M16HA125E_RATIO, | |
82 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
83 | }; | |
84 | ||
85 | static struct emif_regs ddr3_chilisom_emif_reg_data = { | |
86 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, | |
87 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, | |
88 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, | |
89 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, | |
90 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, | |
91 | .ocp_config = 0x00141414, | |
92 | .zq_config = MT41K256M16HA125E_ZQ_CFG, | |
93 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, | |
94 | }; | |
95 | ||
96 | void chilisom_spl_board_init(void) | |
97 | { | |
98 | int mpu_vdd; | |
99 | int usb_cur_lim; | |
100 | ||
101 | enable_i2c0_pin_mux(); | |
102 | ||
103 | /* Get the frequency */ | |
104 | dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); | |
105 | ||
106 | ||
107 | if (i2c_probe(TPS65217_CHIP_PM)) | |
108 | return; | |
109 | ||
110 | /* | |
111 | * Increase USB current limit to 1300mA or 1800mA and set | |
112 | * the MPU voltage controller as needed. | |
113 | */ | |
114 | if (dpll_mpu_opp100.m == MPUPLL_M_1000) { | |
115 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; | |
116 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; | |
117 | } else { | |
118 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; | |
119 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; | |
120 | } | |
121 | ||
122 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, | |
123 | TPS65217_POWER_PATH, | |
124 | usb_cur_lim, | |
125 | TPS65217_USB_INPUT_CUR_LIMIT_MASK)) | |
126 | puts("tps65217_reg_write failure\n"); | |
127 | ||
128 | /* Set DCDC3 (CORE) voltage to 1.125V */ | |
129 | if (tps65217_voltage_update(TPS65217_DEFDCDC3, | |
130 | TPS65217_DCDC_VOLT_SEL_1125MV)) { | |
131 | puts("tps65217_voltage_update failure\n"); | |
132 | return; | |
133 | } | |
134 | /* Set CORE Frequencies to OPP100 */ | |
135 | do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); | |
136 | ||
137 | /* Set DCDC2 (MPU) voltage */ | |
138 | if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { | |
139 | puts("tps65217_voltage_update failure\n"); | |
140 | return; | |
141 | } | |
142 | ||
143 | /* Set LDO3 to 1.8V and LDO4 to 3.3V */ | |
144 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, | |
145 | TPS65217_DEFLS1, | |
146 | TPS65217_LDO_VOLTAGE_OUT_1_8, | |
147 | TPS65217_LDO_MASK)) | |
148 | puts("tps65217_reg_write failure\n"); | |
149 | ||
150 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, | |
151 | TPS65217_DEFLS2, | |
152 | TPS65217_LDO_VOLTAGE_OUT_3_3, | |
153 | TPS65217_LDO_MASK)) | |
154 | puts("tps65217_reg_write failure\n"); | |
155 | ||
156 | /* Set MPU Frequency to what we detected now that voltages are set */ | |
157 | do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); | |
158 | } | |
159 | ||
160 | #define OSC (V_OSCK/1000000) | |
161 | const struct dpll_params dpll_ddr_chilisom = { | |
162 | 400, OSC-1, 1, -1, -1, -1, -1}; | |
163 | ||
164 | const struct dpll_params *get_dpll_ddr_params(void) | |
165 | { | |
166 | return &dpll_ddr_chilisom; | |
167 | } | |
168 | ||
169 | const struct ctrl_ioregs ioregs_chilisom = { | |
170 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
171 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
172 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
173 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
174 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
175 | }; | |
176 | ||
177 | void sdram_init(void) | |
178 | { | |
179 | config_ddr(400, &ioregs_chilisom, | |
180 | &ddr3_chilisom_data, | |
181 | &ddr3_chilisom_cmd_ctrl_data, | |
182 | &ddr3_chilisom_emif_reg_data, 0); | |
183 | } | |
184 | ||
a2ac2b96 | 185 | #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |