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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2ae610f0 A |
2 | /* |
3 | * EMIF programming | |
4 | * | |
5 | * (C) Copyright 2010 | |
6 | * Texas Instruments, <www.ti.com> | |
7 | * | |
8 | * Aneesh V <aneesh@ti.com> | |
2ae610f0 A |
9 | */ |
10 | ||
d678a59d | 11 | #include <common.h> |
db41d65a | 12 | #include <hang.h> |
9b4a205f | 13 | #include <init.h> |
f7ae49fc | 14 | #include <log.h> |
5e6267af | 15 | #include <net.h> |
bb772a59 | 16 | #include <asm/emif.h> |
af1d002f | 17 | #include <asm/arch/clock.h> |
2ae610f0 A |
18 | #include <asm/arch/sys_proto.h> |
19 | #include <asm/omap_common.h> | |
501f0ef3 | 20 | #include <asm/omap_sec_common.h> |
2ae610f0 | 21 | #include <asm/utils.h> |
25476382 | 22 | #include <linux/compiler.h> |
650fda93 | 23 | #include <asm/ti-common/ti-edma3.h> |
c05ed00a | 24 | #include <linux/delay.h> |
2ae610f0 | 25 | |
86021143 LV |
26 | static int emif1_enabled = -1, emif2_enabled = -1; |
27 | ||
38f25b12 LV |
28 | void set_lpmode_selfrefresh(u32 base) |
29 | { | |
30 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
31 | u32 reg; | |
32 | ||
33 | reg = readl(&emif->emif_pwr_mgmt_ctrl); | |
34 | reg &= ~EMIF_REG_LP_MODE_MASK; | |
35 | reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; | |
36 | reg &= ~EMIF_REG_SR_TIM_MASK; | |
37 | writel(reg, &emif->emif_pwr_mgmt_ctrl); | |
38 | ||
39 | /* dummy read for the new SR_TIM to be loaded */ | |
40 | readl(&emif->emif_pwr_mgmt_ctrl); | |
41 | } | |
42 | ||
7c97b715 | 43 | void force_emif_self_refresh(void) |
38f25b12 LV |
44 | { |
45 | set_lpmode_selfrefresh(EMIF1_BASE); | |
663f6fca LV |
46 | if (!is_dra72x()) |
47 | set_lpmode_selfrefresh(EMIF2_BASE); | |
38f25b12 LV |
48 | } |
49 | ||
bb772a59 | 50 | inline u32 emif_num(u32 base) |
2ae610f0 | 51 | { |
bb772a59 | 52 | if (base == EMIF1_BASE) |
2ae610f0 | 53 | return 1; |
bb772a59 | 54 | else if (base == EMIF2_BASE) |
2ae610f0 A |
55 | return 2; |
56 | else | |
57 | return 0; | |
58 | } | |
59 | ||
60 | static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) | |
61 | { | |
62 | u32 mr; | |
63 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
64 | ||
bb772a59 | 65 | mr_addr |= cs << EMIF_REG_CS_SHIFT; |
2ae610f0 A |
66 | writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
67 | if (omap_revision() == OMAP4430_ES2_0) | |
68 | mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); | |
69 | else | |
70 | mr = readl(&emif->emif_lpddr2_mode_reg_data); | |
71 | debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), | |
72 | cs, mr_addr, mr); | |
55c12849 SS |
73 | if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && |
74 | ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && | |
75 | ((mr & 0xff000000) >> 24) == (mr & 0xff)) | |
76 | return mr & 0xff; | |
77 | else | |
78 | return mr; | |
2ae610f0 A |
79 | } |
80 | ||
81 | static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) | |
82 | { | |
83 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
84 | ||
bb772a59 | 85 | mr_addr |= cs << EMIF_REG_CS_SHIFT; |
2ae610f0 A |
86 | writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); |
87 | writel(mr_val, &emif->emif_lpddr2_mode_reg_data); | |
88 | } | |
89 | ||
90 | void emif_reset_phy(u32 base) | |
91 | { | |
92 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
93 | u32 iodft; | |
94 | ||
95 | iodft = readl(&emif->emif_iodft_tlgc); | |
bb772a59 | 96 | iodft |= EMIF_REG_RESET_PHY_MASK; |
2ae610f0 A |
97 | writel(iodft, &emif->emif_iodft_tlgc); |
98 | } | |
99 | ||
100 | static void do_lpddr2_init(u32 base, u32 cs) | |
101 | { | |
102 | u32 mr_addr; | |
e05a4f1f | 103 | const struct lpddr2_mr_regs *mr_regs; |
2ae610f0 | 104 | |
e05a4f1f | 105 | get_lpddr2_mr_regs(&mr_regs); |
2ae610f0 A |
106 | /* Wait till device auto initialization is complete */ |
107 | while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) | |
108 | ; | |
e05a4f1f | 109 | set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); |
2ae610f0 A |
110 | /* |
111 | * tZQINIT = 1 us | |
112 | * Enough loops assuming a maximum of 2GHz | |
113 | */ | |
f4010734 | 114 | |
2ae610f0 | 115 | sdelay(2000); |
f4010734 | 116 | |
e05a4f1f LV |
117 | set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); |
118 | set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); | |
f4010734 | 119 | |
2ae610f0 A |
120 | /* |
121 | * Enable refresh along with writing MR2 | |
122 | * Encoding of RL in MR2 is (RL - 2) | |
123 | */ | |
bb772a59 | 124 | mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; |
e05a4f1f | 125 | set_mr(base, cs, mr_addr, mr_regs->mr2); |
f4010734 | 126 | |
e05a4f1f LV |
127 | if (mr_regs->mr3 > 0) |
128 | set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); | |
2ae610f0 A |
129 | } |
130 | ||
131 | static void lpddr2_init(u32 base, const struct emif_regs *regs) | |
132 | { | |
133 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
134 | ||
135 | /* Not NVM */ | |
bb772a59 | 136 | clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); |
2ae610f0 A |
137 | |
138 | /* | |
139 | * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM | |
140 | * when EMIF_SDRAM_CONFIG register is written | |
141 | */ | |
bb772a59 | 142 | setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); |
2ae610f0 A |
143 | |
144 | /* | |
145 | * Set the SDRAM_CONFIG and PHY_CTRL for the | |
146 | * un-locked frequency & default RL | |
147 | */ | |
148 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
0474fb0e | 149 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
f4010734 | 150 | |
25476382 | 151 | do_ext_phy_settings(base, regs); |
2ae610f0 A |
152 | |
153 | do_lpddr2_init(base, CS0); | |
bb772a59 | 154 | if (regs->sdram_config & EMIF_REG_EBANK_MASK) |
2ae610f0 A |
155 | do_lpddr2_init(base, CS1); |
156 | ||
157 | writel(regs->sdram_config, &emif->emif_sdram_config); | |
158 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); | |
159 | ||
160 | /* Enable refresh now */ | |
bb772a59 | 161 | clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); |
2ae610f0 | 162 | |
25476382 S |
163 | } |
164 | ||
165 | __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) | |
166 | { | |
2ae610f0 A |
167 | } |
168 | ||
bb772a59 | 169 | void emif_update_timings(u32 base, const struct emif_regs *regs) |
2ae610f0 A |
170 | { |
171 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
172 | ||
de095474 LV |
173 | if (!is_dra7xx()) |
174 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); | |
175 | else | |
176 | writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); | |
177 | ||
2ae610f0 A |
178 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); |
179 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); | |
180 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); | |
181 | if (omap_revision() == OMAP4430_ES1_0) { | |
182 | /* ES1 bug EMIF should be in force idle during freq_update */ | |
183 | writel(0, &emif->emif_pwr_mgmt_ctrl); | |
184 | } else { | |
185 | writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); | |
186 | writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); | |
187 | } | |
188 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); | |
189 | writel(regs->zq_config, &emif->emif_zq_config); | |
190 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); | |
191 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); | |
924eb369 | 192 | |
3ac8c0bf | 193 | if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { |
bb772a59 S |
194 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, |
195 | &emif->emif_l3_config); | |
196 | } else if (omap_revision() >= OMAP4460_ES1_0) { | |
924eb369 A |
197 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, |
198 | &emif->emif_l3_config); | |
199 | } else { | |
200 | writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, | |
201 | &emif->emif_l3_config); | |
2ae610f0 A |
202 | } |
203 | } | |
204 | ||
f5af0827 | 205 | #ifndef CONFIG_OMAP44XX |
6c70935d | 206 | static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) |
784ab7c5 LV |
207 | { |
208 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
209 | ||
210 | /* keep sdram in self-refresh */ | |
211 | writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) | |
212 | & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); | |
213 | __udelay(130); | |
214 | ||
215 | /* | |
216 | * Set invert_clkout (if activated)--DDR_PHYCTRL_1 | |
6c70935d S |
217 | * Invert clock adds an additional half cycle delay on the |
218 | * command interface. The additional half cycle, is usually | |
219 | * meant to enable leveling in the situation that DQS is later | |
220 | * than CK on the board.It also helps provide some additional | |
221 | * margin for leveling. | |
784ab7c5 | 222 | */ |
6c70935d S |
223 | writel(regs->emif_ddr_phy_ctlr_1, |
224 | &emif->emif_ddr_phy_ctrl_1); | |
225 | ||
226 | writel(regs->emif_ddr_phy_ctlr_1, | |
227 | &emif->emif_ddr_phy_ctrl_1_shdw); | |
784ab7c5 LV |
228 | __udelay(130); |
229 | ||
230 | writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) | |
6c70935d | 231 | & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); |
784ab7c5 LV |
232 | |
233 | /* Launch Full leveling */ | |
234 | writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); | |
235 | ||
236 | /* Wait till full leveling is complete */ | |
237 | readl(&emif->emif_rd_wr_lvl_ctl); | |
6c70935d | 238 | __udelay(130); |
784ab7c5 LV |
239 | |
240 | /* Read data eye leveling no of samples */ | |
241 | config_data_eye_leveling_samples(base); | |
242 | ||
6c70935d S |
243 | /* |
244 | * Launch 8 incremental WR_LVL- to compensate for | |
245 | * PHY limitation. | |
246 | */ | |
247 | writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, | |
248 | &emif->emif_rd_wr_lvl_ctl); | |
249 | ||
784ab7c5 LV |
250 | __udelay(130); |
251 | ||
252 | /* Launch Incremental leveling */ | |
253 | writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); | |
6c70935d | 254 | __udelay(130); |
784ab7c5 LV |
255 | } |
256 | ||
6213db78 | 257 | static void update_hwleveling_output(u32 base, const struct emif_regs *regs) |
6c70935d | 258 | { |
6213db78 LV |
259 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
260 | u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; | |
e3ce3aa1 | 261 | u32 reg, i, phy; |
6213db78 | 262 | |
e18cd3d7 | 263 | emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6]; |
e3ce3aa1 | 264 | phy = readl(&emif->emif_ddr_phy_ctrl_1); |
6213db78 LV |
265 | |
266 | /* Update PHY_REG_RDDQS_RATIO */ | |
267 | emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; | |
e3ce3aa1 LV |
268 | if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) |
269 | for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { | |
270 | reg = readl(emif_phy_status++); | |
271 | writel(reg, emif_ext_phy_ctrl_reg++); | |
272 | writel(reg, emif_ext_phy_ctrl_reg++); | |
273 | } | |
6213db78 LV |
274 | |
275 | /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ | |
276 | emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; | |
e18cd3d7 | 277 | emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11]; |
e3ce3aa1 LV |
278 | if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) |
279 | for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { | |
280 | reg = readl(emif_phy_status++); | |
281 | writel(reg, emif_ext_phy_ctrl_reg++); | |
282 | writel(reg, emif_ext_phy_ctrl_reg++); | |
283 | } | |
6213db78 LV |
284 | |
285 | /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ | |
286 | emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; | |
e18cd3d7 | 287 | emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16]; |
e3ce3aa1 LV |
288 | if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) |
289 | for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { | |
290 | reg = readl(emif_phy_status++); | |
291 | writel(reg, emif_ext_phy_ctrl_reg++); | |
292 | writel(reg, emif_ext_phy_ctrl_reg++); | |
293 | } | |
6213db78 LV |
294 | |
295 | /* Disable Leveling */ | |
296 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); | |
297 | writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); | |
298 | writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); | |
92b0482c S |
299 | } |
300 | ||
6213db78 LV |
301 | static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) |
302 | { | |
303 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
304 | ||
305 | /* Clear Error Status */ | |
306 | clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, | |
307 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, | |
308 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); | |
309 | ||
310 | clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, | |
311 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, | |
312 | EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); | |
313 | ||
314 | /* Disable refreshed before leveling */ | |
d6927a5d LV |
315 | clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, |
316 | EMIF_REG_INITREF_DIS_MASK); | |
6213db78 LV |
317 | |
318 | /* Start Full leveling */ | |
319 | writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); | |
320 | ||
321 | __udelay(300); | |
322 | ||
323 | /* Check for leveling timeout */ | |
324 | if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { | |
325 | printf("Leveling timeout on EMIF%d\n", emif_num(base)); | |
326 | return; | |
327 | } | |
328 | ||
329 | /* Enable refreshes after leveling */ | |
d6927a5d | 330 | clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); |
6213db78 LV |
331 | |
332 | debug("HW leveling success\n"); | |
333 | /* | |
334 | * Update slave ratios in EXT_PHY_CTRLx registers | |
335 | * as per HW leveling output | |
336 | */ | |
337 | update_hwleveling_output(base, regs); | |
338 | } | |
339 | ||
650fda93 LV |
340 | static void dra7_reset_ddr_data(u32 base, u32 size) |
341 | { | |
342 | #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) | |
343 | enable_edma3_clocks(); | |
344 | ||
345 | edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size); | |
346 | ||
347 | disable_edma3_clocks(); | |
348 | #else | |
349 | memset((void *)base, 0, size); | |
350 | #endif | |
351 | } | |
352 | ||
353 | static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) | |
354 | { | |
355 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
2b2e1573 | 356 | u32 rgn, rgn_start, size, ctrl_reg; |
650fda93 LV |
357 | |
358 | /* ECC available only on dra76x EMIF1 */ | |
359 | if ((base != EMIF1_BASE) || !is_dra76x()) | |
360 | return; | |
361 | ||
362 | if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) { | |
d0a37a5e KB |
363 | /* Disable high-order interleaving */ |
364 | clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); | |
365 | ||
2b2e1573 KB |
366 | #ifdef CONFIG_DRA7XX |
367 | /* Clear the status flags and other history */ | |
368 | writel(readl(&emif->emif_1b_ecc_err_cnt), | |
369 | &emif->emif_1b_ecc_err_cnt); | |
370 | writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1); | |
371 | writel(0x2, &emif->emif_1b_ecc_err_addr_log); | |
372 | writel(0x1, &emif->emif_2b_ecc_err_addr_log); | |
373 | writel(EMIF_INT_WR_ECC_ERR_SYS_MASK | | |
374 | EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK | | |
375 | EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK, | |
376 | &emif->emif_irqstatus_sys); | |
377 | #endif | |
650fda93 LV |
378 | writel(regs->emif_ecc_address_range_1, |
379 | &emif->emif_ecc_address_range_1); | |
380 | writel(regs->emif_ecc_address_range_2, | |
381 | &emif->emif_ecc_address_range_2); | |
2b2e1573 KB |
382 | |
383 | /* Disable RMW and ECC verification for read accesses */ | |
384 | ctrl_reg = (regs->emif_ecc_ctrl_reg & | |
385 | ~EMIF_ECC_REG_RMW_EN_MASK) | | |
386 | EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK; | |
387 | writel(ctrl_reg, &emif->emif_ecc_ctrl_reg); | |
650fda93 LV |
388 | |
389 | /* Set region1 memory with 0 */ | |
ed474ae0 LV |
390 | rgn_start = (regs->emif_ecc_address_range_1 & |
391 | EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; | |
aa6e94de | 392 | rgn = rgn_start + CFG_SYS_SDRAM_BASE; |
650fda93 | 393 | size = (regs->emif_ecc_address_range_1 & |
ed474ae0 | 394 | EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; |
650fda93 LV |
395 | |
396 | if (regs->emif_ecc_ctrl_reg & | |
397 | EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) | |
398 | dra7_reset_ddr_data(rgn, size); | |
399 | ||
400 | /* Set region2 memory with 0 */ | |
ed474ae0 LV |
401 | rgn_start = (regs->emif_ecc_address_range_2 & |
402 | EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; | |
aa6e94de | 403 | rgn = rgn_start + CFG_SYS_SDRAM_BASE; |
650fda93 | 404 | size = (regs->emif_ecc_address_range_2 & |
ed474ae0 | 405 | EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; |
650fda93 LV |
406 | |
407 | if (regs->emif_ecc_ctrl_reg & | |
408 | EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) | |
409 | dra7_reset_ddr_data(rgn, size); | |
410 | ||
2b2e1573 KB |
411 | /* Default value enables RMW and ECC verification */ |
412 | writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg); | |
650fda93 LV |
413 | } |
414 | } | |
415 | ||
6213db78 LV |
416 | static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) |
417 | { | |
418 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
419 | ||
4571c519 | 420 | if (warm_reset()) { |
6213db78 | 421 | emif_reset_phy(base); |
4571c519 LV |
422 | writel(0x0, &emif->emif_pwr_mgmt_ctrl); |
423 | } | |
6213db78 LV |
424 | do_ext_phy_settings(base, regs); |
425 | ||
426 | writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, | |
427 | &emif->emif_sdram_ref_ctrl); | |
428 | /* Update timing registers */ | |
429 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); | |
430 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); | |
431 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); | |
432 | ||
433 | writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); | |
434 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); | |
435 | writel(regs->zq_config, &emif->emif_zq_config); | |
436 | writel(regs->temp_alert_config, &emif->emif_temp_alert_config); | |
437 | writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); | |
438 | writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); | |
439 | ||
440 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); | |
441 | writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); | |
442 | ||
443 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); | |
444 | ||
445 | writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); | |
446 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
447 | ||
448 | __udelay(1000); | |
449 | ||
450 | writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); | |
451 | ||
650fda93 LV |
452 | if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) { |
453 | /* | |
454 | * Perform Dummy ECC setup just to allow hardware | |
455 | * leveling of ECC memories | |
456 | */ | |
457 | if (is_dra76x() && (base == EMIF1_BASE) && | |
458 | (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) { | |
459 | writel(0, &emif->emif_ecc_address_range_1); | |
460 | writel(0, &emif->emif_ecc_address_range_2); | |
461 | writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK | | |
462 | EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK, | |
463 | &emif->emif_ecc_ctrl_reg); | |
464 | } | |
465 | ||
6213db78 | 466 | dra7_ddr3_leveling(base, regs); |
650fda93 LV |
467 | |
468 | /* Disable ECC */ | |
469 | if (is_dra76x()) | |
470 | writel(0, &emif->emif_ecc_ctrl_reg); | |
471 | } | |
472 | ||
473 | /* Enable ECC as necessary */ | |
474 | dra7_enable_ecc(base, regs); | |
6213db78 LV |
475 | } |
476 | ||
477 | static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) | |
784ab7c5 LV |
478 | { |
479 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
784ab7c5 | 480 | |
802bb57a LV |
481 | writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); |
482 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
784ab7c5 LV |
483 | /* |
484 | * Set SDRAM_CONFIG and PHY control registers to locked frequency | |
485 | * and RL =7. As the default values of the Mode Registers are not | |
486 | * defined, contents of mode Registers must be fully initialized. | |
487 | * H/W takes care of this initialization | |
488 | */ | |
784ab7c5 LV |
489 | writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); |
490 | ||
491 | /* Update timing registers */ | |
492 | writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); | |
493 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); | |
494 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); | |
495 | ||
784ab7c5 LV |
496 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); |
497 | ||
6213db78 LV |
498 | writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); |
499 | writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
500 | do_ext_phy_settings(base, regs); | |
784ab7c5 | 501 | |
784ab7c5 | 502 | writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); |
6213db78 LV |
503 | omap5_ddr3_leveling(base, regs); |
504 | } | |
784ab7c5 | 505 | |
6213db78 LV |
506 | static void ddr3_init(u32 base, const struct emif_regs *regs) |
507 | { | |
508 | if (is_omap54xx()) | |
509 | omap5_ddr3_init(base, regs); | |
510 | else | |
511 | dra7_ddr3_init(base, regs); | |
784ab7c5 | 512 | } |
f5af0827 | 513 | #endif |
784ab7c5 | 514 | |
095aea29 A |
515 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
516 | #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) | |
517 | ||
095aea29 A |
518 | /* |
519 | * Organization and refresh requirements for LPDDR2 devices of different | |
520 | * types and densities. Derived from JESD209-2 section 2.4 | |
521 | */ | |
522 | const struct lpddr2_addressing addressing_table[] = { | |
523 | /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ | |
524 | {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ | |
525 | {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ | |
526 | {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ | |
527 | {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ | |
528 | {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ | |
529 | {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ | |
530 | {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ | |
531 | {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ | |
532 | {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ | |
533 | {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ | |
534 | }; | |
535 | ||
536 | static const u32 lpddr2_density_2_size_in_mbytes[] = { | |
537 | 8, /* 64Mb */ | |
538 | 16, /* 128Mb */ | |
539 | 32, /* 256Mb */ | |
540 | 64, /* 512Mb */ | |
541 | 128, /* 1Gb */ | |
542 | 256, /* 2Gb */ | |
543 | 512, /* 4Gb */ | |
544 | 1024, /* 8Gb */ | |
545 | 2048, /* 16Gb */ | |
546 | 4096 /* 32Gb */ | |
547 | }; | |
548 | ||
549 | /* | |
550 | * Calculate the period of DDR clock from frequency value and set the | |
551 | * denominator and numerator in global variables for easy access later | |
552 | */ | |
553 | static void set_ddr_clk_period(u32 freq) | |
554 | { | |
555 | /* | |
556 | * period = 1/freq | |
557 | * period_in_ns = 10^9/freq | |
558 | */ | |
559 | *T_num = 1000000000; | |
560 | *T_den = freq; | |
561 | cancel_out(T_num, T_den, 200); | |
562 | ||
563 | } | |
564 | ||
565 | /* | |
566 | * Convert time in nano seconds to number of cycles of DDR clock | |
567 | */ | |
568 | static inline u32 ns_2_cycles(u32 ns) | |
569 | { | |
570 | return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); | |
571 | } | |
572 | ||
573 | /* | |
574 | * ns_2_cycles with the difference that the time passed is 2 times the actual | |
575 | * value(to avoid fractions). The cycles returned is for the original value of | |
576 | * the timing parameter | |
577 | */ | |
578 | static inline u32 ns_x2_2_cycles(u32 ns) | |
579 | { | |
580 | return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); | |
581 | } | |
582 | ||
583 | /* | |
584 | * Find addressing table index based on the device's type(S2 or S4) and | |
585 | * density | |
586 | */ | |
587 | s8 addressing_table_index(u8 type, u8 density, u8 width) | |
588 | { | |
589 | u8 index; | |
590 | if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) | |
591 | return -1; | |
592 | ||
593 | /* | |
594 | * Look at the way ADDR_TABLE_INDEX* values have been defined | |
595 | * in emif.h compared to LPDDR2_DENSITY_* values | |
596 | * The table is layed out in the increasing order of density | |
597 | * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed | |
598 | * at the end | |
599 | */ | |
600 | if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) | |
601 | index = ADDR_TABLE_INDEX1GS2; | |
602 | else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) | |
603 | index = ADDR_TABLE_INDEX2GS2; | |
604 | else | |
605 | index = density; | |
606 | ||
607 | debug("emif: addressing table index %d\n", index); | |
608 | ||
609 | return index; | |
610 | } | |
611 | ||
612 | /* | |
613 | * Find the the right timing table from the array of timing | |
614 | * tables of the device using DDR clock frequency | |
615 | */ | |
616 | static const struct lpddr2_ac_timings *get_timings_table(const struct | |
d679a529 | 617 | lpddr2_ac_timings *const *device_timings, |
095aea29 A |
618 | u32 freq) |
619 | { | |
620 | u32 i, temp, freq_nearest; | |
621 | const struct lpddr2_ac_timings *timings = 0; | |
622 | ||
623 | emif_assert(freq <= MAX_LPDDR2_FREQ); | |
624 | emif_assert(device_timings); | |
625 | ||
626 | /* | |
627 | * Start with the maximum allowed frequency - that is always safe | |
628 | */ | |
629 | freq_nearest = MAX_LPDDR2_FREQ; | |
630 | /* | |
631 | * Find the timings table that has the max frequency value: | |
632 | * i. Above or equal to the DDR frequency - safe | |
633 | * ii. The lowest that satisfies condition (i) - optimal | |
634 | */ | |
635 | for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { | |
636 | temp = device_timings[i]->max_freq; | |
637 | if ((temp >= freq) && (temp <= freq_nearest)) { | |
638 | freq_nearest = temp; | |
639 | timings = device_timings[i]; | |
640 | } | |
641 | } | |
642 | debug("emif: timings table: %d\n", freq_nearest); | |
643 | return timings; | |
644 | } | |
645 | ||
646 | /* | |
647 | * Finds the value of emif_sdram_config_reg | |
648 | * All parameters are programmed based on the device on CS0. | |
649 | * If there is a device on CS1, it will be same as that on CS0 or | |
650 | * it will be NVM. We don't support NVM yet. | |
651 | * If cs1_device pointer is NULL it is assumed that there is no device | |
652 | * on CS1 | |
653 | */ | |
654 | static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, | |
655 | const struct lpddr2_device_details *cs1_device, | |
656 | const struct lpddr2_addressing *addressing, | |
657 | u8 RL) | |
658 | { | |
659 | u32 config_reg = 0; | |
660 | ||
bb772a59 | 661 | config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; |
095aea29 | 662 | config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << |
bb772a59 | 663 | EMIF_REG_IBANK_POS_SHIFT; |
095aea29 | 664 | |
bb772a59 | 665 | config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; |
095aea29 | 666 | |
bb772a59 | 667 | config_reg |= RL << EMIF_REG_CL_SHIFT; |
095aea29 A |
668 | |
669 | config_reg |= addressing->row_sz[cs0_device->io_width] << | |
bb772a59 | 670 | EMIF_REG_ROWSIZE_SHIFT; |
095aea29 | 671 | |
bb772a59 | 672 | config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; |
095aea29 A |
673 | |
674 | config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << | |
bb772a59 | 675 | EMIF_REG_EBANK_SHIFT; |
095aea29 A |
676 | |
677 | config_reg |= addressing->col_sz[cs0_device->io_width] << | |
bb772a59 | 678 | EMIF_REG_PAGESIZE_SHIFT; |
095aea29 A |
679 | |
680 | return config_reg; | |
681 | } | |
682 | ||
683 | static u32 get_sdram_ref_ctrl(u32 freq, | |
684 | const struct lpddr2_addressing *addressing) | |
685 | { | |
686 | u32 ref_ctrl = 0, val = 0, freq_khz; | |
687 | freq_khz = freq / 1000; | |
688 | /* | |
689 | * refresh rate to be set is 'tREFI * freq in MHz | |
690 | * division by 10000 to account for khz and x10 in t_REFI_us_x10 | |
691 | */ | |
692 | val = addressing->t_REFI_us_x10 * freq_khz / 10000; | |
bb772a59 | 693 | ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; |
095aea29 A |
694 | |
695 | return ref_ctrl; | |
696 | } | |
697 | ||
698 | static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, | |
699 | const struct lpddr2_min_tck *min_tck, | |
700 | const struct lpddr2_addressing *addressing) | |
701 | { | |
702 | u32 tim1 = 0, val = 0; | |
703 | val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; | |
bb772a59 | 704 | tim1 |= val << EMIF_REG_T_WTR_SHIFT; |
095aea29 A |
705 | |
706 | if (addressing->num_banks == BANKS8) | |
707 | val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / | |
708 | (4 * (*T_num)) - 1; | |
709 | else | |
710 | val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; | |
711 | ||
bb772a59 | 712 | tim1 |= val << EMIF_REG_T_RRD_SHIFT; |
095aea29 A |
713 | |
714 | val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; | |
bb772a59 | 715 | tim1 |= val << EMIF_REG_T_RC_SHIFT; |
095aea29 A |
716 | |
717 | val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; | |
bb772a59 | 718 | tim1 |= val << EMIF_REG_T_RAS_SHIFT; |
095aea29 A |
719 | |
720 | val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; | |
bb772a59 | 721 | tim1 |= val << EMIF_REG_T_WR_SHIFT; |
095aea29 A |
722 | |
723 | val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; | |
bb772a59 | 724 | tim1 |= val << EMIF_REG_T_RCD_SHIFT; |
095aea29 A |
725 | |
726 | val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; | |
bb772a59 | 727 | tim1 |= val << EMIF_REG_T_RP_SHIFT; |
095aea29 A |
728 | |
729 | return tim1; | |
730 | } | |
731 | ||
732 | static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, | |
733 | const struct lpddr2_min_tck *min_tck) | |
734 | { | |
735 | u32 tim2 = 0, val = 0; | |
736 | val = max(min_tck->tCKE, timings->tCKE) - 1; | |
bb772a59 | 737 | tim2 |= val << EMIF_REG_T_CKE_SHIFT; |
095aea29 A |
738 | |
739 | val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; | |
bb772a59 | 740 | tim2 |= val << EMIF_REG_T_RTP_SHIFT; |
095aea29 A |
741 | |
742 | /* | |
743 | * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the | |
744 | * same value | |
745 | */ | |
746 | val = ns_2_cycles(timings->tXSR) - 1; | |
bb772a59 S |
747 | tim2 |= val << EMIF_REG_T_XSRD_SHIFT; |
748 | tim2 |= val << EMIF_REG_T_XSNR_SHIFT; | |
095aea29 A |
749 | |
750 | val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; | |
bb772a59 | 751 | tim2 |= val << EMIF_REG_T_XP_SHIFT; |
095aea29 A |
752 | |
753 | return tim2; | |
754 | } | |
755 | ||
756 | static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, | |
757 | const struct lpddr2_min_tck *min_tck, | |
758 | const struct lpddr2_addressing *addressing) | |
759 | { | |
760 | u32 tim3 = 0, val = 0; | |
761 | val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); | |
bb772a59 | 762 | tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; |
095aea29 A |
763 | |
764 | val = ns_2_cycles(timings->tRFCab) - 1; | |
bb772a59 | 765 | tim3 |= val << EMIF_REG_T_RFC_SHIFT; |
095aea29 A |
766 | |
767 | val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; | |
bb772a59 | 768 | tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; |
095aea29 A |
769 | |
770 | val = ns_2_cycles(timings->tZQCS) - 1; | |
bb772a59 | 771 | tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; |
095aea29 A |
772 | |
773 | val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; | |
bb772a59 | 774 | tim3 |= val << EMIF_REG_T_CKESR_SHIFT; |
095aea29 A |
775 | |
776 | return tim3; | |
777 | } | |
778 | ||
779 | static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, | |
780 | const struct lpddr2_addressing *addressing, | |
781 | u8 volt_ramp) | |
782 | { | |
783 | u32 zq = 0, val = 0; | |
784 | if (volt_ramp) | |
785 | val = | |
786 | EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / | |
787 | addressing->t_REFI_us_x10; | |
788 | else | |
789 | val = | |
790 | EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / | |
791 | addressing->t_REFI_us_x10; | |
bb772a59 | 792 | zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; |
095aea29 | 793 | |
bb772a59 | 794 | zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; |
095aea29 | 795 | |
bb772a59 | 796 | zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; |
095aea29 | 797 | |
bb772a59 | 798 | zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; |
095aea29 A |
799 | |
800 | /* | |
801 | * Assuming that two chipselects have a single calibration resistor | |
802 | * If there are indeed two calibration resistors, then this flag should | |
803 | * be enabled to take advantage of dual calibration feature. | |
804 | * This data should ideally come from board files. But considering | |
805 | * that none of the boards today have calibration resistors per CS, | |
806 | * it would be an unnecessary overhead. | |
807 | */ | |
bb772a59 | 808 | zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; |
095aea29 | 809 | |
bb772a59 | 810 | zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; |
095aea29 | 811 | |
bb772a59 | 812 | zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; |
095aea29 A |
813 | |
814 | return zq; | |
815 | } | |
816 | ||
817 | static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, | |
818 | const struct lpddr2_addressing *addressing, | |
819 | u8 is_derated) | |
820 | { | |
821 | u32 alert = 0, interval; | |
822 | interval = | |
823 | TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; | |
824 | if (is_derated) | |
825 | interval *= 4; | |
bb772a59 | 826 | alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; |
095aea29 | 827 | |
bb772a59 | 828 | alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; |
095aea29 | 829 | |
bb772a59 | 830 | alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; |
095aea29 | 831 | |
bb772a59 | 832 | alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; |
095aea29 | 833 | |
bb772a59 | 834 | alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; |
095aea29 | 835 | |
bb772a59 | 836 | alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; |
095aea29 A |
837 | |
838 | return alert; | |
839 | } | |
840 | ||
841 | static u32 get_read_idle_ctrl_reg(u8 volt_ramp) | |
842 | { | |
843 | u32 idle = 0, val = 0; | |
844 | if (volt_ramp) | |
924eb369 | 845 | val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; |
095aea29 A |
846 | else |
847 | /*Maximum value in normal conditions - suggested by hw team */ | |
848 | val = 0x1FF; | |
bb772a59 | 849 | idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; |
095aea29 | 850 | |
bb772a59 | 851 | idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; |
095aea29 A |
852 | |
853 | return idle; | |
854 | } | |
855 | ||
856 | static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) | |
857 | { | |
858 | u32 phy = 0, val = 0; | |
859 | ||
bb772a59 | 860 | phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; |
095aea29 A |
861 | |
862 | if (freq <= 100000000) | |
863 | val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; | |
864 | else if (freq <= 200000000) | |
865 | val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; | |
866 | else | |
867 | val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; | |
bb772a59 | 868 | phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; |
095aea29 A |
869 | |
870 | /* Other fields are constant magic values. Hardcode them together */ | |
871 | phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << | |
bb772a59 | 872 | EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; |
095aea29 A |
873 | |
874 | return phy; | |
875 | } | |
876 | ||
d3d82e9f | 877 | static u32 get_emif_mem_size(u32 base) |
095aea29 A |
878 | { |
879 | u32 size_mbytes = 0, temp; | |
d3d82e9f LV |
880 | struct emif_device_details dev_details; |
881 | struct lpddr2_device_details cs0_dev_details, cs1_dev_details; | |
882 | u32 emif_nr = emif_num(base); | |
095aea29 | 883 | |
d3d82e9f LV |
884 | emif_reset_phy(base); |
885 | dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, | |
886 | &cs0_dev_details); | |
887 | dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, | |
888 | &cs1_dev_details); | |
889 | emif_reset_phy(base); | |
095aea29 | 890 | |
d3d82e9f LV |
891 | if (dev_details.cs0_device_details) { |
892 | temp = dev_details.cs0_device_details->density; | |
095aea29 A |
893 | size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; |
894 | } | |
895 | ||
d3d82e9f LV |
896 | if (dev_details.cs1_device_details) { |
897 | temp = dev_details.cs1_device_details->density; | |
095aea29 A |
898 | size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; |
899 | } | |
900 | /* convert to bytes */ | |
901 | return size_mbytes << 20; | |
902 | } | |
903 | ||
904 | /* Gets the encoding corresponding to a given DMM section size */ | |
905 | u32 get_dmm_section_size_map(u32 section_size) | |
906 | { | |
907 | /* | |
908 | * Section size mapping: | |
909 | * 0x0: 16-MiB section | |
910 | * 0x1: 32-MiB section | |
911 | * 0x2: 64-MiB section | |
912 | * 0x3: 128-MiB section | |
913 | * 0x4: 256-MiB section | |
914 | * 0x5: 512-MiB section | |
915 | * 0x6: 1-GiB section | |
916 | * 0x7: 2-GiB section | |
917 | */ | |
918 | section_size >>= 24; /* divide by 16 MB */ | |
919 | return log_2_n_round_down(section_size); | |
920 | } | |
921 | ||
922 | static void emif_calculate_regs( | |
923 | const struct emif_device_details *emif_dev_details, | |
924 | u32 freq, struct emif_regs *regs) | |
925 | { | |
926 | u32 temp, sys_freq; | |
927 | const struct lpddr2_addressing *addressing; | |
928 | const struct lpddr2_ac_timings *timings; | |
929 | const struct lpddr2_min_tck *min_tck; | |
930 | const struct lpddr2_device_details *cs0_dev_details = | |
931 | emif_dev_details->cs0_device_details; | |
932 | const struct lpddr2_device_details *cs1_dev_details = | |
933 | emif_dev_details->cs1_device_details; | |
934 | const struct lpddr2_device_timings *cs0_dev_timings = | |
935 | emif_dev_details->cs0_device_timings; | |
936 | ||
937 | emif_assert(emif_dev_details); | |
938 | emif_assert(regs); | |
939 | /* | |
940 | * You can not have a device on CS1 without one on CS0 | |
941 | * So configuring EMIF without a device on CS0 doesn't | |
942 | * make sense | |
943 | */ | |
944 | emif_assert(cs0_dev_details); | |
945 | emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); | |
946 | /* | |
947 | * If there is a device on CS1 it should be same type as CS0 | |
948 | * (or NVM. But NVM is not supported in this driver yet) | |
949 | */ | |
950 | emif_assert((cs1_dev_details == NULL) || | |
951 | (cs1_dev_details->type == LPDDR2_TYPE_NVM) || | |
952 | (cs0_dev_details->type == cs1_dev_details->type)); | |
953 | emif_assert(freq <= MAX_LPDDR2_FREQ); | |
954 | ||
955 | set_ddr_clk_period(freq); | |
956 | ||
957 | /* | |
958 | * The device on CS0 is used for all timing calculations | |
959 | * There is only one set of registers for timings per EMIF. So, if the | |
960 | * second CS(CS1) has a device, it should have the same timings as the | |
961 | * device on CS0 | |
962 | */ | |
963 | timings = get_timings_table(cs0_dev_timings->ac_timings, freq); | |
964 | emif_assert(timings); | |
965 | min_tck = cs0_dev_timings->min_tck; | |
966 | ||
967 | temp = addressing_table_index(cs0_dev_details->type, | |
968 | cs0_dev_details->density, | |
969 | cs0_dev_details->io_width); | |
970 | ||
971 | emif_assert((temp >= 0)); | |
972 | addressing = &(addressing_table[temp]); | |
973 | emif_assert(addressing); | |
974 | ||
975 | sys_freq = get_sys_clk_freq(); | |
976 | ||
977 | regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, | |
978 | cs1_dev_details, | |
979 | addressing, RL_BOOT); | |
980 | ||
981 | regs->sdram_config = get_sdram_config_reg(cs0_dev_details, | |
982 | cs1_dev_details, | |
983 | addressing, RL_FINAL); | |
984 | ||
985 | regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); | |
986 | ||
987 | regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); | |
988 | ||
989 | regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); | |
990 | ||
991 | regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); | |
992 | ||
993 | regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); | |
994 | ||
995 | regs->temp_alert_config = | |
996 | get_temp_alert_config(cs1_dev_details, addressing, 0); | |
997 | ||
998 | regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, | |
999 | LPDDR2_VOLTAGE_STABLE); | |
1000 | ||
1001 | regs->emif_ddr_phy_ctlr_1_init = | |
1002 | get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); | |
1003 | ||
1004 | regs->emif_ddr_phy_ctlr_1 = | |
1005 | get_ddr_phy_ctrl_1(freq, RL_FINAL); | |
1006 | ||
1007 | regs->freq = freq; | |
1008 | ||
1009 | print_timing_reg(regs->sdram_config_init); | |
1010 | print_timing_reg(regs->sdram_config); | |
1011 | print_timing_reg(regs->ref_ctrl); | |
1012 | print_timing_reg(regs->sdram_tim1); | |
1013 | print_timing_reg(regs->sdram_tim2); | |
1014 | print_timing_reg(regs->sdram_tim3); | |
1015 | print_timing_reg(regs->read_idle_ctrl); | |
1016 | print_timing_reg(regs->temp_alert_config); | |
1017 | print_timing_reg(regs->zq_config); | |
1018 | print_timing_reg(regs->emif_ddr_phy_ctlr_1); | |
1019 | print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); | |
1020 | } | |
1021 | #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ | |
1022 | ||
1e463866 A |
1023 | #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION |
1024 | const char *get_lpddr2_type(u8 type_id) | |
1025 | { | |
1026 | switch (type_id) { | |
1027 | case LPDDR2_TYPE_S4: | |
1028 | return "LPDDR2-S4"; | |
1029 | case LPDDR2_TYPE_S2: | |
1030 | return "LPDDR2-S2"; | |
1031 | default: | |
1032 | return NULL; | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | const char *get_lpddr2_io_width(u8 width_id) | |
1037 | { | |
1038 | switch (width_id) { | |
1039 | case LPDDR2_IO_WIDTH_8: | |
1040 | return "x8"; | |
1041 | case LPDDR2_IO_WIDTH_16: | |
1042 | return "x16"; | |
1043 | case LPDDR2_IO_WIDTH_32: | |
1044 | return "x32"; | |
1045 | default: | |
1046 | return NULL; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | const char *get_lpddr2_manufacturer(u32 manufacturer) | |
1051 | { | |
1052 | switch (manufacturer) { | |
1053 | case LPDDR2_MANUFACTURER_SAMSUNG: | |
1054 | return "Samsung"; | |
1055 | case LPDDR2_MANUFACTURER_QIMONDA: | |
1056 | return "Qimonda"; | |
1057 | case LPDDR2_MANUFACTURER_ELPIDA: | |
1058 | return "Elpida"; | |
1059 | case LPDDR2_MANUFACTURER_ETRON: | |
1060 | return "Etron"; | |
1061 | case LPDDR2_MANUFACTURER_NANYA: | |
1062 | return "Nanya"; | |
1063 | case LPDDR2_MANUFACTURER_HYNIX: | |
1064 | return "Hynix"; | |
1065 | case LPDDR2_MANUFACTURER_MOSEL: | |
1066 | return "Mosel"; | |
1067 | case LPDDR2_MANUFACTURER_WINBOND: | |
1068 | return "Winbond"; | |
1069 | case LPDDR2_MANUFACTURER_ESMT: | |
1070 | return "ESMT"; | |
1071 | case LPDDR2_MANUFACTURER_SPANSION: | |
1072 | return "Spansion"; | |
1073 | case LPDDR2_MANUFACTURER_SST: | |
1074 | return "SST"; | |
1075 | case LPDDR2_MANUFACTURER_ZMOS: | |
1076 | return "ZMOS"; | |
1077 | case LPDDR2_MANUFACTURER_INTEL: | |
1078 | return "Intel"; | |
1079 | case LPDDR2_MANUFACTURER_NUMONYX: | |
1080 | return "Numonyx"; | |
1081 | case LPDDR2_MANUFACTURER_MICRON: | |
1082 | return "Micron"; | |
1083 | default: | |
1084 | return NULL; | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | static void display_sdram_details(u32 emif_nr, u32 cs, | |
1089 | struct lpddr2_device_details *device) | |
1090 | { | |
1091 | const char *mfg_str; | |
1092 | const char *type_str; | |
1093 | char density_str[10]; | |
1094 | u32 density; | |
1095 | ||
1096 | debug("EMIF%d CS%d\t", emif_nr, cs); | |
1097 | ||
1098 | if (!device) { | |
1099 | debug("None\n"); | |
1100 | return; | |
1101 | } | |
1102 | ||
1103 | mfg_str = get_lpddr2_manufacturer(device->manufacturer); | |
1104 | type_str = get_lpddr2_type(device->type); | |
1105 | ||
1106 | density = lpddr2_density_2_size_in_mbytes[device->density]; | |
1107 | if ((density / 1024 * 1024) == density) { | |
1108 | density /= 1024; | |
1109 | sprintf(density_str, "%d GB", density); | |
1110 | } else | |
1111 | sprintf(density_str, "%d MB", density); | |
1112 | if (mfg_str && type_str) | |
1113 | debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); | |
1114 | } | |
1115 | ||
1116 | static u8 is_lpddr2_sdram_present(u32 base, u32 cs, | |
1117 | struct lpddr2_device_details *lpddr2_device) | |
1118 | { | |
1119 | u32 mr = 0, temp; | |
1120 | ||
1121 | mr = get_mr(base, cs, LPDDR2_MR0); | |
1122 | if (mr > 0xFF) { | |
1123 | /* Mode register value bigger than 8 bit */ | |
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; | |
1128 | if (temp) { | |
1129 | /* Not SDRAM */ | |
1130 | return 0; | |
1131 | } | |
1132 | temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; | |
1133 | ||
1134 | if (temp) { | |
1135 | /* DNV supported - But DNV is only supported for NVM */ | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | mr = get_mr(base, cs, LPDDR2_MR4); | |
1140 | if (mr > 0xFF) { | |
1141 | /* Mode register value bigger than 8 bit */ | |
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | mr = get_mr(base, cs, LPDDR2_MR5); | |
ad0878a7 | 1146 | if (mr > 0xFF) { |
1e463866 A |
1147 | /* Mode register value bigger than 8 bit */ |
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | if (!get_lpddr2_manufacturer(mr)) { | |
1152 | /* Manufacturer not identified */ | |
1153 | return 0; | |
1154 | } | |
1155 | lpddr2_device->manufacturer = mr; | |
1156 | ||
1157 | mr = get_mr(base, cs, LPDDR2_MR6); | |
1158 | if (mr >= 0xFF) { | |
1159 | /* Mode register value bigger than 8 bit */ | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | mr = get_mr(base, cs, LPDDR2_MR7); | |
1164 | if (mr >= 0xFF) { | |
1165 | /* Mode register value bigger than 8 bit */ | |
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | mr = get_mr(base, cs, LPDDR2_MR8); | |
1170 | if (mr >= 0xFF) { | |
1171 | /* Mode register value bigger than 8 bit */ | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; | |
1176 | if (!get_lpddr2_type(temp)) { | |
1177 | /* Not SDRAM */ | |
1178 | return 0; | |
1179 | } | |
1180 | lpddr2_device->type = temp; | |
1181 | ||
1182 | temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; | |
1183 | if (temp > LPDDR2_DENSITY_32Gb) { | |
1184 | /* Density not supported */ | |
1185 | return 0; | |
1186 | } | |
1187 | lpddr2_device->density = temp; | |
1188 | ||
1189 | temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; | |
1190 | if (!get_lpddr2_io_width(temp)) { | |
1191 | /* IO width unsupported value */ | |
1192 | return 0; | |
1193 | } | |
1194 | lpddr2_device->io_width = temp; | |
1195 | ||
1196 | /* | |
1197 | * If all the above tests pass we should | |
1198 | * have a device on this chip-select | |
1199 | */ | |
1200 | return 1; | |
1201 | } | |
1202 | ||
025bc425 | 1203 | struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, |
1e463866 A |
1204 | struct lpddr2_device_details *lpddr2_dev_details) |
1205 | { | |
1206 | u32 phy; | |
bb772a59 S |
1207 | u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; |
1208 | ||
1e463866 A |
1209 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
1210 | ||
1211 | if (!lpddr2_dev_details) | |
1212 | return NULL; | |
1213 | ||
1214 | /* Do the minimum init for mode register accesses */ | |
784229cc | 1215 | if (!(running_from_sdram() || warm_reset())) { |
1e463866 A |
1216 | phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); |
1217 | writel(phy, &emif->emif_ddr_phy_ctrl_1); | |
1218 | } | |
1219 | ||
1220 | if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) | |
1221 | return NULL; | |
1222 | ||
1223 | display_sdram_details(emif_num(base), cs, lpddr2_dev_details); | |
1224 | ||
1225 | return lpddr2_dev_details; | |
1226 | } | |
1e463866 A |
1227 | #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ |
1228 | ||
2ae610f0 A |
1229 | static void do_sdram_init(u32 base) |
1230 | { | |
1231 | const struct emif_regs *regs; | |
1232 | u32 in_sdram, emif_nr; | |
1233 | ||
1234 | debug(">>do_sdram_init() %x\n", base); | |
1235 | ||
1236 | in_sdram = running_from_sdram(); | |
bb772a59 | 1237 | emif_nr = (base == EMIF1_BASE) ? 1 : 2; |
2ae610f0 | 1238 | |
095aea29 | 1239 | #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
2ae610f0 A |
1240 | emif_get_reg_dump(emif_nr, ®s); |
1241 | if (!regs) { | |
1242 | debug("EMIF: reg dump not provided\n"); | |
1243 | return; | |
1244 | } | |
095aea29 A |
1245 | #else |
1246 | /* | |
1247 | * The user has not provided the register values. We need to | |
1248 | * calculate it based on the timings and the DDR frequency | |
1249 | */ | |
1250 | struct emif_device_details dev_details; | |
1251 | struct emif_regs calculated_regs; | |
1252 | ||
1253 | /* | |
1254 | * Get device details: | |
1255 | * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set | |
1256 | * - Obtained from user otherwise | |
1257 | */ | |
1258 | struct lpddr2_device_details cs0_dev_details, cs1_dev_details; | |
025bc425 | 1259 | emif_reset_phy(base); |
4324c118 | 1260 | dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, |
025bc425 | 1261 | &cs0_dev_details); |
4324c118 | 1262 | dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, |
025bc425 A |
1263 | &cs1_dev_details); |
1264 | emif_reset_phy(base); | |
095aea29 A |
1265 | |
1266 | /* Return if no devices on this EMIF */ | |
1267 | if (!dev_details.cs0_device_details && | |
1268 | !dev_details.cs1_device_details) { | |
095aea29 A |
1269 | return; |
1270 | } | |
1271 | ||
095aea29 A |
1272 | /* |
1273 | * Get device timings: | |
1274 | * - Default timings specified by JESD209-2 if | |
1275 | * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set | |
1276 | * - Obtained from user otherwise | |
1277 | */ | |
1278 | emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, | |
1279 | &dev_details.cs1_device_timings); | |
1280 | ||
1281 | /* Calculate the register values */ | |
2e5ba489 | 1282 | emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); |
095aea29 A |
1283 | regs = &calculated_regs; |
1284 | #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ | |
2ae610f0 A |
1285 | |
1286 | /* | |
f5af0827 | 1287 | * Initializing the DDR device can not happen from SDRAM. |
2ae610f0 A |
1288 | * Changing the timing registers in EMIF can happen(going from one |
1289 | * OPP to another) | |
1290 | */ | |
c997da5c | 1291 | if (!in_sdram && (!warm_reset() || is_dra7xx())) { |
7c352cd3 TR |
1292 | if (emif_sdram_type(regs->sdram_config) == |
1293 | EMIF_SDRAM_TYPE_LPDDR2) | |
784ab7c5 | 1294 | lpddr2_init(base, regs); |
f5af0827 | 1295 | #ifndef CONFIG_OMAP44XX |
784ab7c5 LV |
1296 | else |
1297 | ddr3_init(base, regs); | |
f5af0827 | 1298 | #endif |
784ab7c5 | 1299 | } |
c9592e3c | 1300 | #ifdef CONFIG_OMAP54XX |
7c352cd3 | 1301 | if (warm_reset() && (emif_sdram_type(regs->sdram_config) == |
c997da5c | 1302 | EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { |
166e5cc6 LV |
1303 | set_lpmode_selfrefresh(base); |
1304 | emif_reset_phy(base); | |
6213db78 | 1305 | omap5_ddr3_leveling(base, regs); |
166e5cc6 | 1306 | } |
f5af0827 | 1307 | #endif |
2ae610f0 A |
1308 | |
1309 | /* Write to the shadow registers */ | |
1310 | emif_update_timings(base, regs); | |
1311 | ||
1312 | debug("<<do_sdram_init() %x\n", base); | |
1313 | } | |
1314 | ||
bb772a59 | 1315 | void emif_post_init_config(u32 base) |
2ae610f0 A |
1316 | { |
1317 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; | |
bb772a59 S |
1318 | u32 omap_rev = omap_revision(); |
1319 | ||
2ae610f0 | 1320 | /* reset phy on ES2.0 */ |
bb772a59 | 1321 | if (omap_rev == OMAP4430_ES2_0) |
2ae610f0 A |
1322 | emif_reset_phy(base); |
1323 | ||
1324 | /* Put EMIF back in smart idle on ES1.0 */ | |
bb772a59 | 1325 | if (omap_rev == OMAP4430_ES1_0) |
2ae610f0 A |
1326 | writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); |
1327 | } | |
1328 | ||
bb772a59 | 1329 | void dmm_init(u32 base) |
2ae610f0 A |
1330 | { |
1331 | const struct dmm_lisa_map_regs *lisa_map_regs; | |
86021143 | 1332 | u32 i, section, valid; |
2ae610f0 | 1333 | |
095aea29 | 1334 | #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
2ae610f0 | 1335 | emif_get_dmm_regs(&lisa_map_regs); |
095aea29 A |
1336 | #else |
1337 | u32 emif1_size, emif2_size, mapped_size, section_map = 0; | |
1338 | u32 section_cnt, sys_addr; | |
1339 | struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; | |
1340 | ||
1341 | mapped_size = 0; | |
1342 | section_cnt = 3; | |
aa6e94de | 1343 | sys_addr = CFG_SYS_SDRAM_BASE; |
d3d82e9f LV |
1344 | emif1_size = get_emif_mem_size(EMIF1_BASE); |
1345 | emif2_size = get_emif_mem_size(EMIF2_BASE); | |
095aea29 A |
1346 | debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); |
1347 | ||
1348 | if (!emif1_size && !emif2_size) | |
1349 | return; | |
1350 | ||
1351 | /* symmetric interleaved section */ | |
1352 | if (emif1_size && emif2_size) { | |
1353 | mapped_size = min(emif1_size, emif2_size); | |
1354 | section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; | |
bb772a59 | 1355 | section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; |
095aea29 A |
1356 | /* only MSB */ |
1357 | section_map |= (sys_addr >> 24) << | |
bb772a59 | 1358 | EMIF_SYS_ADDR_SHIFT; |
095aea29 | 1359 | section_map |= get_dmm_section_size_map(mapped_size * 2) |
bb772a59 | 1360 | << EMIF_SYS_SIZE_SHIFT; |
095aea29 A |
1361 | lis_map_regs_calculated.dmm_lisa_map_3 = section_map; |
1362 | emif1_size -= mapped_size; | |
1363 | emif2_size -= mapped_size; | |
1364 | sys_addr += (mapped_size * 2); | |
1365 | section_cnt--; | |
1366 | } | |
1367 | ||
1368 | /* | |
1369 | * Single EMIF section(we can have a maximum of 1 single EMIF | |
1370 | * section- either EMIF1 or EMIF2 or none, but not both) | |
1371 | */ | |
1372 | if (emif1_size) { | |
1373 | section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; | |
1374 | section_map |= get_dmm_section_size_map(emif1_size) | |
bb772a59 | 1375 | << EMIF_SYS_SIZE_SHIFT; |
095aea29 A |
1376 | /* only MSB */ |
1377 | section_map |= (mapped_size >> 24) << | |
bb772a59 | 1378 | EMIF_SDRC_ADDR_SHIFT; |
095aea29 | 1379 | /* only MSB */ |
bb772a59 | 1380 | section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; |
095aea29 A |
1381 | section_cnt--; |
1382 | } | |
1383 | if (emif2_size) { | |
1384 | section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; | |
1385 | section_map |= get_dmm_section_size_map(emif2_size) << | |
bb772a59 | 1386 | EMIF_SYS_SIZE_SHIFT; |
095aea29 | 1387 | /* only MSB */ |
bb772a59 | 1388 | section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; |
095aea29 | 1389 | /* only MSB */ |
bb772a59 | 1390 | section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; |
095aea29 A |
1391 | section_cnt--; |
1392 | } | |
1393 | ||
1394 | if (section_cnt == 2) { | |
1395 | /* Only 1 section - either symmetric or single EMIF */ | |
1396 | lis_map_regs_calculated.dmm_lisa_map_3 = section_map; | |
1397 | lis_map_regs_calculated.dmm_lisa_map_2 = 0; | |
1398 | lis_map_regs_calculated.dmm_lisa_map_1 = 0; | |
1399 | } else { | |
1400 | /* 2 sections - 1 symmetric, 1 single EMIF */ | |
1401 | lis_map_regs_calculated.dmm_lisa_map_2 = section_map; | |
1402 | lis_map_regs_calculated.dmm_lisa_map_1 = 0; | |
1403 | } | |
1404 | ||
1405 | /* TRAP for invalid TILER mappings in section 0 */ | |
1406 | lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; | |
2ae610f0 | 1407 | |
e3f53104 LV |
1408 | if (omap_revision() >= OMAP4460_ES1_0) |
1409 | lis_map_regs_calculated.is_ma_present = 1; | |
1410 | ||
095aea29 A |
1411 | lisa_map_regs = &lis_map_regs_calculated; |
1412 | #endif | |
2ae610f0 A |
1413 | struct dmm_lisa_map_regs *hw_lisa_map_regs = |
1414 | (struct dmm_lisa_map_regs *)base; | |
1415 | ||
1416 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); | |
1417 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); | |
1418 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); | |
1419 | writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); | |
1420 | ||
1421 | writel(lisa_map_regs->dmm_lisa_map_3, | |
1422 | &hw_lisa_map_regs->dmm_lisa_map_3); | |
1423 | writel(lisa_map_regs->dmm_lisa_map_2, | |
1424 | &hw_lisa_map_regs->dmm_lisa_map_2); | |
1425 | writel(lisa_map_regs->dmm_lisa_map_1, | |
1426 | &hw_lisa_map_regs->dmm_lisa_map_1); | |
1427 | writel(lisa_map_regs->dmm_lisa_map_0, | |
1428 | &hw_lisa_map_regs->dmm_lisa_map_0); | |
924eb369 | 1429 | |
7831419d | 1430 | if (lisa_map_regs->is_ma_present) { |
924eb369 | 1431 | hw_lisa_map_regs = |
bb772a59 | 1432 | (struct dmm_lisa_map_regs *)MA_BASE; |
924eb369 A |
1433 | |
1434 | writel(lisa_map_regs->dmm_lisa_map_3, | |
1435 | &hw_lisa_map_regs->dmm_lisa_map_3); | |
1436 | writel(lisa_map_regs->dmm_lisa_map_2, | |
1437 | &hw_lisa_map_regs->dmm_lisa_map_2); | |
1438 | writel(lisa_map_regs->dmm_lisa_map_1, | |
1439 | &hw_lisa_map_regs->dmm_lisa_map_1); | |
1440 | writel(lisa_map_regs->dmm_lisa_map_0, | |
1441 | &hw_lisa_map_regs->dmm_lisa_map_0); | |
29c20ba2 LV |
1442 | |
1443 | setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); | |
924eb369 | 1444 | } |
86021143 LV |
1445 | |
1446 | /* | |
1447 | * EMIF should be configured only when | |
1448 | * memory is mapped on it. Using emif1_enabled | |
1449 | * and emif2_enabled variables for this. | |
1450 | */ | |
1451 | emif1_enabled = 0; | |
1452 | emif2_enabled = 0; | |
1453 | for (i = 0; i < 4; i++) { | |
1454 | section = __raw_readl(DMM_BASE + i*4); | |
1455 | valid = (section & EMIF_SDRC_MAP_MASK) >> | |
1456 | (EMIF_SDRC_MAP_SHIFT); | |
1457 | if (valid == 3) { | |
1458 | emif1_enabled = 1; | |
1459 | emif2_enabled = 1; | |
1460 | break; | |
dbf02eca FB |
1461 | } |
1462 | ||
1463 | if (valid == 1) | |
86021143 | 1464 | emif1_enabled = 1; |
dbf02eca FB |
1465 | |
1466 | if (valid == 2) | |
86021143 | 1467 | emif2_enabled = 1; |
86021143 | 1468 | } |
2ae610f0 A |
1469 | } |
1470 | ||
54d022e7 S |
1471 | static void do_bug0039_workaround(u32 base) |
1472 | { | |
1473 | u32 val, i, clkctrl; | |
1474 | struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; | |
1475 | const struct read_write_regs *bug_00339_regs; | |
1476 | u32 iterations; | |
1477 | u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; | |
1478 | u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; | |
1479 | ||
1480 | if (is_dra7xx()) | |
1481 | phy_status_base++; | |
1482 | ||
1483 | bug_00339_regs = get_bug_regs(&iterations); | |
1484 | ||
1485 | /* Put EMIF in to idle */ | |
1486 | clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); | |
1487 | __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); | |
1488 | ||
1489 | /* Copy the phy status registers in to phy ctrl shadow registers */ | |
1490 | for (i = 0; i < iterations; i++) { | |
1491 | val = __raw_readl(phy_status_base + | |
1492 | bug_00339_regs[i].read_reg - 1); | |
1493 | ||
1494 | __raw_writel(val, phy_ctrl_base + | |
1495 | ((bug_00339_regs[i].write_reg - 1) << 1)); | |
1496 | ||
1497 | __raw_writel(val, phy_ctrl_base + | |
1498 | (bug_00339_regs[i].write_reg << 1) - 1); | |
1499 | } | |
1500 | ||
1501 | /* Disable leveling */ | |
1502 | writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); | |
1503 | ||
1504 | __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); | |
1505 | } | |
1506 | ||
2ae610f0 A |
1507 | /* |
1508 | * SDRAM initialization: | |
1509 | * SDRAM initialization has two parts: | |
1510 | * 1. Configuring the SDRAM device | |
1511 | * 2. Update the AC timings related parameters in the EMIF module | |
1512 | * (1) should be done only once and should not be done while we are | |
1513 | * running from SDRAM. | |
1514 | * (2) can and should be done more than once if OPP changes. | |
1515 | * Particularly, this may be needed when we boot without SPL and | |
1516 | * and using Configuration Header(CH). ROM code supports only at 50% OPP | |
1517 | * at boot (low power boot). So u-boot has to switch to OPP100 and update | |
1518 | * the frequency. So, | |
1519 | * Doing (1) and (2) makes sense - first time initialization | |
1520 | * Doing (2) and not (1) makes sense - OPP change (when using CH) | |
1521 | * Doing (1) and not (2) doen't make sense | |
1522 | * See do_sdram_init() for the details | |
1523 | */ | |
1524 | void sdram_init(void) | |
1525 | { | |
1526 | u32 in_sdram, size_prog, size_detect; | |
7c352cd3 TR |
1527 | struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; |
1528 | u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); | |
2ae610f0 A |
1529 | |
1530 | debug(">>sdram_init()\n"); | |
1531 | ||
508a58fa | 1532 | if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) |
2ae610f0 A |
1533 | return; |
1534 | ||
1535 | in_sdram = running_from_sdram(); | |
1536 | debug("in_sdram = %d\n", in_sdram); | |
1537 | ||
166e5cc6 LV |
1538 | if (!in_sdram) { |
1539 | if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) | |
01b753ff | 1540 | bypass_dpll((*prcm)->cm_clkmode_dpll_core); |
166e5cc6 | 1541 | else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) |
01b753ff | 1542 | writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); |
753bae8c | 1543 | } |
2ae610f0 | 1544 | |
784229cc | 1545 | if (!in_sdram) |
bb772a59 | 1546 | dmm_init(DMM_BASE); |
784229cc | 1547 | |
86021143 LV |
1548 | if (emif1_enabled) |
1549 | do_sdram_init(EMIF1_BASE); | |
1550 | ||
1551 | if (emif2_enabled) | |
1552 | do_sdram_init(EMIF2_BASE); | |
1553 | ||
784229cc | 1554 | if (!(in_sdram || warm_reset())) { |
86021143 LV |
1555 | if (emif1_enabled) |
1556 | emif_post_init_config(EMIF1_BASE); | |
1557 | if (emif2_enabled) | |
1558 | emif_post_init_config(EMIF2_BASE); | |
2ae610f0 A |
1559 | } |
1560 | ||
1561 | /* for the shadow registers to take effect */ | |
9ca8bfea | 1562 | if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) |
753bae8c | 1563 | freq_update_core(); |
2ae610f0 A |
1564 | |
1565 | /* Do some testing after the init */ | |
1566 | if (!in_sdram) { | |
508a58fa | 1567 | size_prog = omap_sdram_size(); |
41321fd4 S |
1568 | size_prog = log_2_n_round_down(size_prog); |
1569 | size_prog = (1 << size_prog); | |
1570 | ||
aa6e94de | 1571 | size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE, |
2ae610f0 A |
1572 | size_prog); |
1573 | /* Compare with the size programmed */ | |
1574 | if (size_detect != size_prog) { | |
1575 | printf("SDRAM: identified size not same as expected" | |
1576 | " size identified: %x expected: %x\n", | |
1577 | size_detect, | |
1578 | size_prog); | |
1579 | } else | |
1580 | debug("get_ram_size() successful"); | |
1581 | } | |
1582 | ||
501f0ef3 DA |
1583 | #if defined(CONFIG_TI_SECURE_DEVICE) |
1584 | /* | |
1585 | * On HS devices, do static EMIF firewall configuration | |
1586 | * but only do it if not already running in SDRAM | |
1587 | */ | |
1588 | if (!in_sdram) | |
1589 | if (0 != secure_emif_reserve()) | |
1590 | hang(); | |
1591 | ||
1592 | /* On HS devices, ensure static EMIF firewall APIs are locked */ | |
1593 | if (0 != secure_emif_firewall_lock()) | |
1594 | hang(); | |
1595 | #endif | |
1596 | ||
54d022e7 | 1597 | if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && |
f2a1b93b | 1598 | (!in_sdram && !warm_reset()) && (!is_dra7xx())) { |
9fcf3d3a LV |
1599 | if (emif1_enabled) |
1600 | do_bug0039_workaround(EMIF1_BASE); | |
1601 | if (emif2_enabled) | |
1602 | do_bug0039_workaround(EMIF2_BASE); | |
54d022e7 S |
1603 | } |
1604 | ||
2ae610f0 A |
1605 | debug("<<sdram_init()\n"); |
1606 | } |