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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
d34efc76 SS |
2 | /* |
3 | * | |
508a58fa | 4 | * Common functions for OMAP4/5 based boards |
d34efc76 SS |
5 | * |
6 | * (C) Copyright 2010 | |
7 | * Texas Instruments, <www.ti.com> | |
8 | * | |
9 | * Author : | |
10 | * Aneesh V <aneesh@ti.com> | |
11 | * Steve Sakoman <steve@sakoman.com> | |
d34efc76 | 12 | */ |
d678a59d | 13 | #include <common.h> |
01fe1199 | 14 | #include <debug_uart.h> |
7fe32b34 | 15 | #include <event.h> |
40ecdbc6 | 16 | #include <fdtdec.h> |
691d719d | 17 | #include <init.h> |
47f7bcae | 18 | #include <spl.h> |
d34efc76 | 19 | #include <asm/arch/sys_proto.h> |
401d1c4f | 20 | #include <asm/global_data.h> |
1ace4022 | 21 | #include <linux/sizes.h> |
bb772a59 | 22 | #include <asm/emif.h> |
01b753ff | 23 | #include <asm/omap_common.h> |
d4d986ee | 24 | #include <linux/compiler.h> |
de63ac27 | 25 | #include <asm/system.h> |
40ecdbc6 | 26 | #include <dm/root.h> |
de63ac27 | 27 | |
93e3568b NM |
28 | DECLARE_GLOBAL_DATA_PTR; |
29 | ||
469ec1e3 A |
30 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) |
31 | { | |
32 | int i; | |
33 | struct pad_conf_entry *pad = (struct pad_conf_entry *) array; | |
34 | ||
35 | for (i = 0; i < size; i++, pad++) | |
36 | writew(pad->val, base + pad->offset); | |
37 | } | |
38 | ||
469ec1e3 A |
39 | static void set_mux_conf_regs(void) |
40 | { | |
508a58fa | 41 | switch (omap_hw_init_context()) { |
469ec1e3 | 42 | case OMAP_INIT_CONTEXT_SPL: |
3ef56e61 | 43 | set_muxconf_regs(); |
469ec1e3 A |
44 | break; |
45 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: | |
469ec1e3 A |
46 | break; |
47 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: | |
48 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: | |
3ef56e61 | 49 | set_muxconf_regs(); |
469ec1e3 A |
50 | break; |
51 | } | |
52 | } | |
53 | ||
508a58fa | 54 | u32 cortex_rev(void) |
ad577c8a A |
55 | { |
56 | ||
57 | unsigned int rev; | |
58 | ||
59 | /* Read Main ID Register (MIDR) */ | |
60 | asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); | |
61 | ||
62 | return rev; | |
63 | } | |
64 | ||
0ac6db26 | 65 | static void omap_rev_string(void) |
ad577c8a | 66 | { |
508a58fa | 67 | u32 omap_rev = omap_revision(); |
de62688b | 68 | u32 soc_variant = (omap_rev & 0xF0000000) >> 28; |
508a58fa S |
69 | u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; |
70 | u32 major_rev = (omap_rev & 0x00000F00) >> 8; | |
71 | u32 minor_rev = (omap_rev & 0x000000F0) >> 4; | |
ad577c8a | 72 | |
941f2fcc | 73 | const char *sec_s, *package = NULL; |
47c331ed DA |
74 | |
75 | switch (get_device_type()) { | |
76 | case TST_DEVICE: | |
77 | sec_s = "TST"; | |
78 | break; | |
79 | case EMU_DEVICE: | |
80 | sec_s = "EMU"; | |
81 | break; | |
82 | case HS_DEVICE: | |
83 | sec_s = "HS"; | |
84 | break; | |
85 | case GP_DEVICE: | |
86 | sec_s = "GP"; | |
87 | break; | |
88 | default: | |
89 | sec_s = "?"; | |
90 | } | |
91 | ||
941f2fcc LV |
92 | #if defined(CONFIG_DRA7XX) |
93 | if (is_dra76x()) { | |
94 | switch (omap_rev & 0xF) { | |
95 | case DRA762_ABZ_PACKAGE: | |
96 | package = "ABZ"; | |
97 | break; | |
98 | case DRA762_ACD_PACKAGE: | |
99 | default: | |
100 | package = "ACD"; | |
101 | break; | |
102 | } | |
103 | } | |
104 | #endif | |
105 | ||
de62688b LV |
106 | if (soc_variant) |
107 | printf("OMAP"); | |
108 | else | |
109 | printf("DRA"); | |
941f2fcc LV |
110 | printf("%x-%s ES%x.%x", omap_variant, sec_s, major_rev, minor_rev); |
111 | if (package) | |
112 | printf(" %s package\n", package); | |
113 | else | |
114 | puts("\n"); | |
ad577c8a A |
115 | } |
116 | ||
78f455c0 | 117 | #ifdef CONFIG_SPL_BUILD |
861a86f4 TR |
118 | void spl_display_print(void) |
119 | { | |
120 | omap_rev_string(); | |
121 | } | |
78f455c0 S |
122 | #endif |
123 | ||
d4d986ee LV |
124 | void __weak srcomp_enable(void) |
125 | { | |
126 | } | |
127 | ||
d88d6c8c KS |
128 | /** |
129 | * do_board_detect() - Detect board description | |
130 | * | |
131 | * Function to detect board description. This is expected to be | |
132 | * overridden in the SoC family board file where desired. | |
133 | */ | |
134 | void __weak do_board_detect(void) | |
135 | { | |
136 | } | |
137 | ||
61462cd7 K |
138 | /** |
139 | * vcores_init() - Assign omap_vcores based on board | |
140 | * | |
141 | * Function to pick the vcores based on board. This is expected to be | |
142 | * overridden in the SoC family board file where desired. | |
143 | */ | |
144 | void __weak vcores_init(void) | |
145 | { | |
146 | } | |
147 | ||
e850ed82 LV |
148 | void s_init(void) |
149 | { | |
150 | } | |
151 | ||
941f2fcc LV |
152 | /** |
153 | * init_package_revision() - Initialize package revision | |
154 | * | |
155 | * Function to get the pacakage information. This is expected to be | |
156 | * overridden in the SoC family file where desired. | |
157 | */ | |
158 | void __weak init_package_revision(void) | |
159 | { | |
160 | } | |
161 | ||
e850ed82 LV |
162 | /** |
163 | * early_system_init - Does Early system initialization. | |
164 | * | |
165 | * Does early system init of watchdog, muxing, andclocks | |
469ec1e3 | 166 | * Watchdog disable is done always. For the rest what gets done |
e850ed82 LV |
167 | * depends on the boot mode in which this function is executed when |
168 | * 1. SPL running from SRAM | |
169 | * 2. U-Boot running from FLASH | |
170 | * 3. U-Boot loaded to SDRAM by SPL | |
171 | * 4. U-Boot loaded to SDRAM by ROM code using the | |
469ec1e3 A |
172 | * Configuration Header feature |
173 | * Please have a look at the respective functions to see what gets | |
174 | * done in each of these cases | |
175 | * This function is called with SRAM stack. | |
d34efc76 | 176 | */ |
f72d0d4a | 177 | int early_system_init(void) |
d34efc76 | 178 | { |
40ecdbc6 JJH |
179 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) |
180 | int ret; | |
181 | int rescan; | |
182 | #endif | |
508a58fa | 183 | init_omap_revision(); |
01b753ff | 184 | hw_data_init(); |
941f2fcc | 185 | init_package_revision(); |
01b753ff | 186 | |
38f25b12 | 187 | #ifdef CONFIG_SPL_BUILD |
663f6fca | 188 | if (warm_reset()) |
38f25b12 LV |
189 | force_emif_self_refresh(); |
190 | #endif | |
d34efc76 | 191 | watchdog_init(); |
469ec1e3 | 192 | set_mux_conf_regs(); |
bcae7211 | 193 | #ifdef CONFIG_SPL_BUILD |
d4d986ee | 194 | srcomp_enable(); |
4ecfcfaa | 195 | do_io_settings(); |
bcae7211 | 196 | #endif |
93e6253d | 197 | setup_early_clocks(); |
40ecdbc6 | 198 | |
4bd754d8 LV |
199 | #ifdef CONFIG_SPL_BUILD |
200 | /* | |
201 | * Save the boot parameters passed from romcode. | |
202 | * We cannot delay the saving further than this, | |
203 | * to prevent overwrites. | |
204 | */ | |
205 | save_omap_boot_params(); | |
a4d72869 JJH |
206 | spl_early_init(); |
207 | #endif | |
2b30b38b JJH |
208 | do_board_detect(); |
209 | ||
40ecdbc6 JJH |
210 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT) |
211 | /* | |
212 | * Board detection has been done. | |
213 | * Let us see if another dtb wouldn't be a better match | |
214 | * for our board | |
215 | */ | |
216 | ret = fdtdec_resetup(&rescan); | |
217 | if (!ret && rescan) { | |
218 | dm_uninit(); | |
219 | dm_init_and_scan(true); | |
220 | } | |
221 | #endif | |
222 | ||
61462cd7 | 223 | vcores_init(); |
01fe1199 LV |
224 | #ifdef CONFIG_DEBUG_UART_OMAP |
225 | debug_uart_init(); | |
226 | #endif | |
3776801d | 227 | prcm_init(); |
f72d0d4a SG |
228 | |
229 | return 0; | |
7ae8350f SG |
230 | } |
231 | ||
bcae7211 | 232 | #ifdef CONFIG_SPL_BUILD |
7ae8350f SG |
233 | void board_init_f(ulong dummy) |
234 | { | |
e850ed82 | 235 | early_system_init(); |
7b922523 LV |
236 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
237 | board_early_init_f(); | |
238 | #endif | |
bcae7211 A |
239 | /* For regular u-boot sdram_init() is called from dram_init() */ |
240 | sdram_init(); | |
86282798 | 241 | gd->ram_size = omap_sdram_size(); |
d34efc76 | 242 | } |
7ae8350f | 243 | #endif |
d34efc76 | 244 | |
f72d0d4a | 245 | EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, early_system_init); |
e850ed82 | 246 | |
d34efc76 SS |
247 | /* |
248 | * Routine: wait_for_command_complete | |
249 | * Description: Wait for posting to finish on watchdog | |
250 | */ | |
251 | void wait_for_command_complete(struct watchdog *wd_base) | |
252 | { | |
253 | int pending = 1; | |
254 | do { | |
255 | pending = readl(&wd_base->wwps); | |
256 | } while (pending); | |
257 | } | |
258 | ||
259 | /* | |
260 | * Routine: watchdog_init | |
261 | * Description: Shut down watch dogs | |
262 | */ | |
263 | void watchdog_init(void) | |
264 | { | |
265 | struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; | |
266 | ||
267 | writel(WD_UNLOCK1, &wd2_base->wspr); | |
268 | wait_for_command_complete(wd2_base); | |
269 | writel(WD_UNLOCK2, &wd2_base->wspr); | |
270 | } | |
271 | ||
7ca3f9c5 A |
272 | |
273 | /* | |
274 | * This function finds the SDRAM size available in the system | |
275 | * based on DMM section configurations | |
276 | * This is needed because the size of memory installed may be | |
277 | * different on different versions of the board | |
278 | */ | |
508a58fa | 279 | u32 omap_sdram_size(void) |
7ca3f9c5 | 280 | { |
e06e914d S |
281 | u32 section, i, valid; |
282 | u64 sdram_start = 0, sdram_end = 0, addr, | |
d7630da6 | 283 | size, total_size = 0, trap_size = 0, trap_start = 0; |
bb772a59 | 284 | |
7ca3f9c5 | 285 | for (i = 0; i < 4; i++) { |
bb772a59 | 286 | section = __raw_readl(DMM_BASE + i*4); |
e06e914d S |
287 | valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> |
288 | (EMIF_SDRC_ADDRSPC_SHIFT); | |
bb772a59 | 289 | addr = section & EMIF_SYS_ADDR_MASK; |
e06e914d | 290 | |
7ca3f9c5 | 291 | /* See if the address is valid */ |
939911a6 TR |
292 | if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && |
293 | (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { | |
bb772a59 S |
294 | size = ((section & EMIF_SYS_SIZE_MASK) >> |
295 | EMIF_SYS_SIZE_SHIFT); | |
296 | size = 1 << size; | |
297 | size *= SZ_16M; | |
e06e914d S |
298 | |
299 | if (valid != DMM_SDRC_ADDR_SPC_INVALID) { | |
300 | if (!sdram_start || (addr < sdram_start)) | |
301 | sdram_start = addr; | |
302 | if (!sdram_end || ((addr + size) > sdram_end)) | |
303 | sdram_end = addr + size; | |
304 | } else { | |
305 | trap_size = size; | |
d7630da6 | 306 | trap_start = addr; |
e06e914d | 307 | } |
7ca3f9c5 A |
308 | } |
309 | } | |
d7630da6 LV |
310 | |
311 | if ((trap_start >= sdram_start) && (trap_start < sdram_end)) | |
312 | total_size = (sdram_end - sdram_start) - (trap_size); | |
313 | else | |
314 | total_size = sdram_end - sdram_start; | |
bb772a59 | 315 | |
7ca3f9c5 A |
316 | return total_size; |
317 | } | |
318 | ||
319 | ||
d34efc76 SS |
320 | /* |
321 | * Routine: dram_init | |
322 | * Description: sets uboots idea of sdram size | |
323 | */ | |
324 | int dram_init(void) | |
325 | { | |
2ae610f0 | 326 | sdram_init(); |
508a58fa | 327 | gd->ram_size = omap_sdram_size(); |
d34efc76 SS |
328 | return 0; |
329 | } | |
330 | ||
331 | /* | |
332 | * Print board information | |
333 | */ | |
334 | int checkboard(void) | |
335 | { | |
336 | puts(sysinfo.board_string); | |
337 | return 0; | |
338 | } | |
339 | ||
365475e6 | 340 | #if defined(CONFIG_DISPLAY_CPUINFO) |
508a58fa S |
341 | /* |
342 | * Print CPU information | |
343 | */ | |
344 | int print_cpuinfo(void) | |
8b457fa8 | 345 | { |
761ca31e AM |
346 | puts("CPU : "); |
347 | omap_rev_string(); | |
13d4f9bd | 348 | |
508a58fa S |
349 | return 0; |
350 | } | |
365475e6 | 351 | #endif |