[thirdparty/u-boot.git] / arch / arm / mach-omap2 / omap-cache.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * Common functions for OMAP4/5 based boards
 *
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Aneesh V	<aneesh@ti.com>
 *	Steve Sakoman	<steve@sakoman.com>
 */

#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Without LPAE short descriptors are used
 * Set C - Cache Bit3
 * Set B - Buffer Bit2
 * The last 2 bits set to 0b10
 * Do Not set XN bit4
 * So value is 0xe
 *
 * With LPAE cache configuration happens via MAIR0 register
 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
 * 0xFF maps to Cache writeback with Read and Write Allocate set
 * The bits[1:0] should have the value 0b01 for the first level
 * descriptor.
 * So the value is 0xd
 */

#ifdef CONFIG_ARMV7_LPAE
#define ARMV7_DCACHE_POLICY	DCACHE_WRITEALLOC
#else
#define ARMV7_DCACHE_POLICY	DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
#endif

void enable_caches(void)
{

	/* Enable I cache if not enabled */
	if (!icache_status())
		icache_enable();

	dcache_enable();
}

void dram_bank_mmu_setup(int bank)
{
	struct bd_info *bd = gd->bd;
	int	i;

	u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
	u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
	u32 end = start + size;

	debug("%s: bank: %d\n", __func__, bank);
	for (i = start; i < end; i++)
		set_section_dcache(i, ARMV7_DCACHE_POLICY);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7e4154a5 SG	2	/*
	3	*
	4	* Common functions for OMAP4/5 based boards
	5	*
	6	* (C) Copyright 2010
	7	* Texas Instruments, <www.ti.com>
	8	*
	9	* Author :
	10	* Aneesh V <aneesh@ti.com>
	11	* Steve Sakoman <steve@sakoman.com>
7e4154a5 SG	12	*/
7e4154a5 SG	13
d678a59d	14	#include <common.h>
9edefc27	15	#include <cpu_func.h>
f7ae49fc	16	#include <log.h>
7e4154a5	17	#include <asm/cache.h>
401d1c4f	18	#include <asm/global_data.h>
7e4154a5 SG	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
859c70df K	22	/*
	23	* Without LPAE short descriptors are used
	24	* Set C - Cache Bit3
	25	* Set B - Buffer Bit2
	26	* The last 2 bits set to 0b10
	27	* Do Not set XN bit4
	28	* So value is 0xe
	29	*
	30	* With LPAE cache configuration happens via MAIR0 register
	31	* AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
	32	* 0xFF maps to Cache writeback with Read and Write Allocate set
	33	* The bits[1:0] should have the value 0b01 for the first level
	34	* descriptor.
	35	* So the value is 0xd
	36	*/
	37
	38	#ifdef CONFIG_ARMV7_LPAE
	39	#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
	40	#else
	41	#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
	42	#endif
	43
7e4154a5 SG	44	void enable_caches(void)
7e4154a5 SG	45	{
7ce85318 LV	46
	47	/* Enable I cache if not enabled */
	48	if (!icache_status())
	49	icache_enable();
	50
7e4154a5 SG	51	dcache_enable();
	52	}
	53
	54	void dram_bank_mmu_setup(int bank)
	55	{
b75d8dc5	56	struct bd_info *bd = gd->bd;
7e4154a5 SG	57	int i;
7e4154a5 SG	58
c268a9bd K	59	u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
c268a9bd K	60	u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
7e4154a5 SG	61	u32 end = start + size;
	62
	63	debug("%s: bank: %d\n", __func__, bank);
	64	for (i = start; i < end; i++)
859c70df	65	set_section_dcache(i, ARMV7_DCACHE_POLICY);
7e4154a5	66	}