projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 08fc7171 IY |
2 | /* |
| 3 | * This file configures the internal USB PHY in AM35X. | |
| 4 | * | |
| 5 | * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com> | |
| 6 | * | |
| 7 | * Based on omap_phy_internal.c code from Linux by | |
| 8 | * Hema HK <hemahk@ti.com> | |
| 08fc7171 IY |
9 | */ |
| 10 | ||
| d678a59d | 11 | #include <common.h> |
| f7ae49fc | 12 | #include <log.h> |
| 401d1c4f | 13 | #include <dm/device.h> |
| 08fc7171 IY |
14 | #include <asm/io.h> |
| 15 | #include <asm/arch/am35x_def.h> | |
| 16 | ||
| 1cac34ce | 17 | void am35x_musb_reset(struct udevice *dev) |
| 08fc7171 IY |
18 | { |
| 19 | /* Reset the musb interface */ | |
| 20 | clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, | |
| 21 | 0, USBOTGSS_SW_RST); | |
| 22 | clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset, | |
| 23 | USBOTGSS_SW_RST, 0); | |
| 24 | } | |
| 25 | ||
| 1cac34ce | 26 | void am35x_musb_phy_power(struct udevice *dev, u8 on) |
| 08fc7171 IY |
27 | { |
| 28 | unsigned long start = get_timer(0); | |
| 29 | ||
| 30 | if (on) { | |
| 31 | /* | |
| 32 | * Start the on-chip PHY and its PLL. | |
| 33 | */ | |
| 34 | clrsetbits_le32(&am35x_scm_general_regs->devconf2, | |
| 35 | CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN, | |
| 36 | CONF2_PHY_PLLON); | |
| 37 | ||
| 38 | debug("Waiting for PHY clock good...\n"); | |
| 39 | while (!(readl(&am35x_scm_general_regs->devconf2) | |
| 40 | & CONF2_PHYCLKGD)) { | |
| 41 | ||
| 42 | if (get_timer(start) > CONFIG_SYS_HZ / 10) { | |
| 43 | printf("musb PHY clock good timed out\n"); | |
| 44 | break; | |
| 45 | } | |
| 46 | } | |
| 47 | } else { | |
| 48 | /* | |
| 49 | * Power down the on-chip PHY. | |
| 50 | */ | |
| 51 | clrsetbits_le32(&am35x_scm_general_regs->devconf2, | |
| 52 | CONF2_PHY_PLLON, | |
| 53 | CONF2_PHYPWRDN | CONF2_OTGPWRDN); | |
| 54 | } | |
| 55 | } | |
| 56 | ||
| 1cac34ce | 57 | void am35x_musb_clear_irq(struct udevice *dev) |
| 08fc7171 IY |
58 | { |
| 59 | clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr, | |
| 60 | 0, USBOTGSS_INT_CLR); | |
| 61 | readl(&am35x_scm_general_regs->lvl_intr_clr); | |
| 62 | } |