[thirdparty/u-boot.git] / arch / arm / mach-omap2 / omap3 / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 */
#include <common.h>
#include <command.h>
#include <dm.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>

/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif

#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_plat omap34xx_gpio[] = {
	{ 0, OMAP34XX_GPIO1_BASE },
	{ 1, OMAP34XX_GPIO2_BASE },
	{ 2, OMAP34XX_GPIO3_BASE },
	{ 3, OMAP34XX_GPIO4_BASE },
	{ 4, OMAP34XX_GPIO5_BASE },
	{ 5, OMAP34XX_GPIO6_BASE },
};

U_BOOT_DRVINFOS(omap34xx_gpios) = {
	{ "gpio_omap", &omap34xx_gpio[0] },
	{ "gpio_omap", &omap34xx_gpio[1] },
	{ "gpio_omap", &omap34xx_gpio[2] },
	{ "gpio_omap", &omap34xx_gpio[3] },
	{ "gpio_omap", &omap34xx_gpio[4] },
	{ "gpio_omap", &omap34xx_gpio[5] },
};
#endif
#else

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE },
	{ (void *)OMAP34XX_GPIO2_BASE },
	{ (void *)OMAP34XX_GPIO3_BASE },
	{ (void *)OMAP34XX_GPIO4_BASE },
	{ (void *)OMAP34XX_GPIO5_BASE },
	{ (void *)OMAP34XX_GPIO6_BASE },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#endif

void early_system_init(void)
{
	hw_data_init();
}

#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
	!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
static void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
static void secureworld_exit(void)
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
static void try_unlock_memory(void)
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	watchdog_init();
	early_system_init();

	try_unlock_memory();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif
}
#endif

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
	early_system_init();
	omap3_mem_init();
	/*
	* Save the boot parameters passed from romcode.
	* We cannot delay the saving further than this,
	* to prevent overwrites.
	*/
	save_omap_boot_params();
}
#endif

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	omap_die_id_display();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
static void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	setbits_le32(&prcm_base->fclken_wkup, 0x20);
	setbits_le32(&prcm_base->iclken_wkup, 0x20);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
			 char *const argv[])
{
	int hw, strength = 1;

	if (argc < 2 || argc > 3)
		goto usage;

	if (strncmp(argv[1], "hw", 2) == 0) {
		hw = 1;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "bch16", 5) == 0)
				strength = 16;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else if (strncmp(argv[1], "sw", 2) == 0) {
		hw = 0;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else {
		goto usage;
	}

	return -omap_nand_switch_ecc(hw, strength);

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 3, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
	" and 8-bit/16-bit BCH\n"
	"                           ecc calculation (second parameter may"
	" be omitted).\n"
	"nandecc sw               - Switch to NAND software ecc algorithm."
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

void __weak omap3_set_aux_cr_secure(u32 acr)
{
	struct emu_hal_params emu_romcode_params;

	emu_romcode_params.num_params = 1;
	emu_romcode_params.param1 = acr;
	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
			       (u32 *)&emu_romcode_params);
}

void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
				 u32 cpu_rev_comb, u32 cpu_variant,
				 u32 cpu_rev)
{
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);

	/* L2 Cache Auxiliary Control Register is not banked */
}

void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
			  u32 cpu_variant, u32 cpu_rev)
{
	/* Write ACR - affects secure banked bits */
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	else
		omap3_set_aux_cr_secure(acr);

	/* Write ACR - affects non-secure banked bits - some erratas need it */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}


#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;
	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);

}

/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{

	/*
	 * Set L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/*
	 * Clear L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
91eee546 DB	2	/*
	3	*
	4	* Common board functions for OMAP3 based boards.
	5	*
	6	* (C) Copyright 2004-2008
	7	* Texas Instruments, <www.ti.com>
	8	*
	9	* Author :
	10	* Sunil Kumar <sunilsaini05@gmail.com>
	11	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	12	*
	13	* Derived from Beagle Board and 3430 SDP code by
	14	* Richard Woodruff <r-woodruff2@ti.com>
	15	* Syed Mohammed Khasim <khasim@ti.com>
	16	*
91eee546	17	*/
d678a59d	18	#include <common.h>
09140113	19	#include <command.h>
b3f4ca11	20	#include <dm.h>
691d719d	21	#include <init.h>
47f7bcae	22	#include <spl.h>
91eee546 DB	23	#include <asm/io.h>
	24	#include <asm/arch/sys_proto.h>
	25	#include <asm/arch/mem.h>
06e758e7	26	#include <asm/cache.h>
45bf0585	27	#include <asm/armv7.h>
b3f4ca11	28	#include <asm/gpio.h>
bb085b87	29	#include <asm/omap_common.h>
8a87a3d7	30	#include <linux/compiler.h>
91eee546	31
45bf0585	32	/* Declarations */
91eee546	33	extern omap3_sysinfo sysinfo;
57f588be	34	#ifndef CONFIG_SYS_L2CACHE_OFF
45bf0585	35	static void omap3_invalidate_l2_cache_secure(void);
57f588be	36	#endif
91eee546	37
bcee8d67	38	#if CONFIG_IS_ENABLED(DM_GPIO)
33ac2b56 AF	39	#if !CONFIG_IS_ENABLED(OF_CONTROL)
33ac2b56 AF	40	/* Manually initialize GPIO banks when OF_CONTROL doesn't */
8a8d24bd	41	static const struct omap_gpio_plat omap34xx_gpio[] = {
0a9e3405 TR	42	{ 0, OMAP34XX_GPIO1_BASE },
	43	{ 1, OMAP34XX_GPIO2_BASE },
	44	{ 2, OMAP34XX_GPIO3_BASE },
	45	{ 3, OMAP34XX_GPIO4_BASE },
	46	{ 4, OMAP34XX_GPIO5_BASE },
	47	{ 5, OMAP34XX_GPIO6_BASE },
b3f4ca11 SG	48	};
b3f4ca11 SG	49
20e442ab	50	U_BOOT_DRVINFOS(omap34xx_gpios) = {
b3f4ca11 SG	51	{ "gpio_omap", &omap34xx_gpio[0] },
	52	{ "gpio_omap", &omap34xx_gpio[1] },
	53	{ "gpio_omap", &omap34xx_gpio[2] },
	54	{ "gpio_omap", &omap34xx_gpio[3] },
	55	{ "gpio_omap", &omap34xx_gpio[4] },
	56	{ "gpio_omap", &omap34xx_gpio[5] },
	57	};
33ac2b56	58	#endif
b3f4ca11 SG	59	#else
b3f4ca11 SG	60
25223a68	61	static const struct gpio_bank gpio_bank_34xx[6] = {
0a9e3405 TR	62	{ (void *)OMAP34XX_GPIO1_BASE },
	63	{ (void *)OMAP34XX_GPIO2_BASE },
	64	{ (void *)OMAP34XX_GPIO3_BASE },
	65	{ (void *)OMAP34XX_GPIO4_BASE },
	66	{ (void *)OMAP34XX_GPIO5_BASE },
	67	{ (void *)OMAP34XX_GPIO6_BASE },
25223a68 A	68	};
	69
	70	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	71
b3f4ca11 SG	72	#endif
b3f4ca11 SG	73
4f9b15ea AF	74	void early_system_init(void)
	75	{
	76	hw_data_init();
	77	}
	78
a2ac2b96 TR	79	#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
a2ac2b96 TR	80	!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
4f9b15ea	81
91eee546 DB	82	/******************************************************************************
	83	* Routine: secure_unlock
	84	* Description: Setup security registers for access
	85	* (GP Device only)
	86	*****************************************************************************/
4f9b15ea	87	static void secure_unlock_mem(void)
91eee546	88	{
97a099ea DB	89	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	90	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	91	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	92	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	93	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	94
	95	/* Protection Module Register Target APE (PM_RT) */
	96	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	97	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	98	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	99	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	100
	101	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	102	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	103	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	104
	105	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	106	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	107	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	108	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	109
	110	/* IVA Changes */
	111	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	112	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	113	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	114
	115	/* SDRC region 0 public */
	116	writel(UNLOCK_1, &sms_base->rg_att0);
	117	}
	118
	119	/******************************************************************************
	120	* Routine: secureworld_exit()
	121	* Description: If chip is EMU and boot type is external
	122	* configure secure registers and exit secure world
	123	* general use.
	124	*****************************************************************************/
46bf58d9	125	static void secureworld_exit(void)
91eee546 DB	126	{
	127	unsigned long i;
	128
a4958313	129	/* configure non-secure access control register */
91eee546 DB	130	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	131	/* enabling co-processor CP10 and CP11 accesses in NS world */
	132	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	133	/*
	134	* allow allocation of locked TLBs and L2 lines in NS world
	135	* allow use of PLE registers in NS world also
	136	*/
	137	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	138	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	139
	140	/* Enable ASA in ACR register */
	141	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	142	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	143	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	144
	145	/* Exiting secure world */
	146	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	147	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	148	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	149	}
	150
91eee546 DB	151	/******************************************************************************
	152	* Routine: try_unlock_sram()
	153	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	154	* general use.
	155	*****************************************************************************/
1ddd0ed3	156	static void try_unlock_memory(void)
91eee546 DB	157	{
	158	int mode;
	159	int in_sdram = is_running_in_sdram();
	160
	161	/*
	162	* if GP device unlock device SRAM for general use
	163	* secure code breaks for Secure/Emulation device - HS/E/T
	164	*/
	165	mode = get_device_type();
	166	if (mode == GP_DEVICE)
	167	secure_unlock_mem();
	168
	169	/*
	170	* If device is EMU and boot is XIP external booting
	171	* Unlock firewalls and disable L2 and put chip
	172	* out of secure world
	173	*
	174	* Assuming memories are unlocked by the demon who put us in SDRAM
	175	*/
	176	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	177	&& (!in_sdram)) {
	178	secure_unlock_mem();
	179	secureworld_exit();
	180	}
	181
	182	return;
	183	}
	184
	185	/******************************************************************************
	186	* Routine: s_init
	187	* Description: Does early system init of muxing and clocks.
	188	* - Called path is with SRAM stack.
	189	*****************************************************************************/
	190	void s_init(void)
	191	{
91eee546	192	watchdog_init();
00bbe96e	193	early_system_init();
91eee546 DB	194
	195	try_unlock_memory();
	196
45bf0585 A	197	#ifndef CONFIG_SYS_L2CACHE_OFF
	198	/* Invalidate L2-cache from secure mode */
	199	omap3_invalidate_l2_cache_secure();
91eee546	200	#endif
91eee546 DB	201
91eee546 DB	202	set_muxconf_regs();
86623add	203	sdelay(100);
91eee546 DB	204
	205	prcm_init();
	206
	207	per_clocks_enable();
	208
95f87910 G	209	#ifdef CONFIG_USB_EHCI_OMAP
	210	ehci_clocks_enable();
	211	#endif
7ae8350f	212	}
50ef3851	213	#endif
95f87910	214
7ae8350f SG	215	#ifdef CONFIG_SPL_BUILD
	216	void board_init_f(ulong dummy)
	217	{
00bbe96e	218	early_system_init();
6c84e712	219	omap3_mem_init();
c3bec547 AF	220	/*
	221	* Save the boot parameters passed from romcode.
	222	* We cannot delay the saving further than this,
	223	* to prevent overwrites.
	224	*/
	225	save_omap_boot_params();
91eee546	226	}
7ae8350f	227	#endif
91eee546	228
8a87a3d7 TR	229	/*
	230	* Routine: misc_init_r
	231	* Description: A basic misc_init_r that just displays the die ID
	232	*/
	233	int __weak misc_init_r(void)
	234	{
679f82c3	235	omap_die_id_display();
8a87a3d7 TR	236
	237	return 0;
	238	}
	239
91eee546 DB	240	/******************************************************************************
	241	* Routine: wait_for_command_complete
	242	* Description: Wait for posting to finish on watchdog
	243	*****************************************************************************/
98431d58	244	static void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	245	{
	246	int pending = 1;
	247	do {
	248	pending = readl(&wd_base->wwps);
	249	} while (pending);
	250	}
	251
	252	/******************************************************************************
	253	* Routine: watchdog_init
	254	* Description: Shut down watch dogs
	255	*****************************************************************************/
	256	void watchdog_init(void)
	257	{
97a099ea DB	258	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	259	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	260
	261	/*
	262	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	263	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	264	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	265	* should not be running and does not generate a PRCM reset.
	266	*/
	267
e7300f46 WD	268	setbits_le32(&prcm_base->fclken_wkup, 0x20);
e7300f46 WD	269	setbits_le32(&prcm_base->iclken_wkup, 0x20);
91eee546 DB	270	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	271
	272	writel(WD_UNLOCK1, &wd2_base->wspr);
	273	wait_for_command_complete(wd2_base);
	274	writel(WD_UNLOCK2, &wd2_base->wspr);
	275	}
	276
91eee546 DB	277	/******************************************************************************
	278	* Dummy function to handle errors for EABI incompatibility
	279	*****************************************************************************/
	280	void abort(void)
	281	{
	282	}
	283
bb085b87	284	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	285	/******************************************************************************
	286	* OMAP3 specific command to switch between NAND HW and SW ecc
	287	*****************************************************************************/
09140113 SG	288	static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	289	char *const argv[])
91eee546	290	{
50075153 LM	291	int hw, strength = 1;
50075153 LM	292
da634ae3	293	if (argc < 2 \|\| argc > 3)
91eee546	294	goto usage;
da634ae3 AB	295
da634ae3 AB	296	if (strncmp(argv[1], "hw", 2) == 0) {
50075153 LM	297	hw = 1;
	298	if (argc == 3) {
	299	if (strncmp(argv[2], "bch8", 4) == 0)
	300	strength = 8;
3a504d96	301	else if (strncmp(argv[2], "bch16", 5) == 0)
50075153 LM	302	strength = 16;
50075153 LM	303	else if (strncmp(argv[2], "hamming", 7) != 0)
da634ae3 AB	304	goto usage;
	305	}
	306	} else if (strncmp(argv[1], "sw", 2) == 0) {
50075153 LM	307	hw = 0;
	308	if (argc == 3) {
	309	if (strncmp(argv[2], "bch8", 4) == 0)
	310	strength = 8;
	311	else if (strncmp(argv[2], "hamming", 7) != 0)
b050898e AC	312	goto usage;
b050898e AC	313	}
da634ae3	314	} else {
91eee546	315	goto usage;
da634ae3	316	}
91eee546	317
50075153	318	return -omap_nand_switch_ecc(hw, strength);
91eee546 DB	319
91eee546 DB	320	usage:
36003268	321	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	322	return 1;
	323	}
	324
	325	U_BOOT_CMD(
da634ae3	326	nandecc, 3, 1, do_switch_ecc,
a93c92cd	327	"switch OMAP3 NAND ECC calculation algorithm",
3a504d96 HS	328	"hw [hamming\|bch8\|bch16] - Switch between NAND hardware 1-bit hamming"
3a504d96 HS	329	" and 8-bit/16-bit BCH\n"
da634ae3 AB	330	" ecc calculation (second parameter may"
	331	" be omitted).\n"
	332	"nandecc sw - Switch to NAND software ecc algorithm."
a89c33db	333	);
91eee546	334
bb085b87	335	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	336
	337	#ifdef CONFIG_DISPLAY_BOARDINFO
	338	/**
	339	* Print board information
	340	*/
	341	int checkboard (void)
	342	{
	343	char *mem_s ;
	344
	345	if (is_mem_sdr())
	346	mem_s = "mSDR";
	347	else
	348	mem_s = "LPDDR";
	349
	350	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	351	sysinfo.nand_string);
	352
	353	return 0;
	354	}
	355	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	356
	357	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	358	{
	359	u32 i, num_params = *parameters;
	360	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	361
	362	/*
	363	* copy the parameters to an un-cached area to avoid coherency
	364	* issues
	365	*/
	366	for (i = 0; i < num_params; i++) {
	367	__raw_writel(*parameters, sram_scratch_space);
	368	parameters++;
	369	sram_scratch_space++;
	370	}
	371
	372	/* Now make the PPA call */
	373	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	374	}
	375
cdef0b3f	376	void __weak omap3_set_aux_cr_secure(u32 acr)
45bf0585	377	{
cdef0b3f NM	378	struct emu_hal_params emu_romcode_params;
	379
	380	emu_romcode_params.num_params = 1;
	381	emu_romcode_params.param1 = acr;
	382	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	383	(u32 *)&emu_romcode_params);
45bf0585 A	384	}
45bf0585 A	385
19a75b8c SS	386	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
	387	u32 cpu_rev_comb, u32 cpu_variant,
	388	u32 cpu_rev)
	389	{
	390	if (get_device_type() == GP_DEVICE)
	391	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
	392
	393	/* L2 Cache Auxiliary Control Register is not banked */
	394	}
	395
cdef0b3f NM	396	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
cdef0b3f NM	397	u32 cpu_variant, u32 cpu_rev)
45bf0585	398	{
cdef0b3f NM	399	/* Write ACR - affects secure banked bits */
	400	if (get_device_type() == GP_DEVICE)
	401	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	402	else
	403	omap3_set_aux_cr_secure(acr);
c6f90e14	404
cdef0b3f NM	405	/* Write ACR - affects non-secure banked bits - some erratas need it */
cdef0b3f NM	406	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
45bf0585 A	407	}
45bf0585 A	408
cdef0b3f	409
45bf0585	410	#ifndef CONFIG_SYS_L2CACHE_OFF
57f588be TR	411	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	412	{
	413	u32 acr;
	414
	415	/* Read ACR */
	416	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	417	acr &= ~clear_bits;
	418	acr \|= set_bits;
cdef0b3f	419	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
57f588be	420
57f588be TR	421	}
57f588be TR	422
45bf0585 A	423	/* Invalidate the entire L2 cache from secure mode */
	424	static void omap3_invalidate_l2_cache_secure(void)
	425	{
	426	if (get_device_type() == GP_DEVICE) {
49ec9490	427	omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
45bf0585 A	428	} else {
	429	struct emu_hal_params emu_romcode_params;
	430	emu_romcode_params.num_params = 1;
	431	emu_romcode_params.param1 = 0;
	432	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	433	(u32 *)&emu_romcode_params);
	434	}
	435	}
	436
	437	void v7_outer_cache_enable(void)
	438	{
45bf0585 A	439
45bf0585 A	440	/*
cdef0b3f	441	* Set L2EN
45bf0585 A	442	* On some revisions L2EN bit is banked on some revisions it's not
	443	* No harm in setting both banked bits(in fact this is required
	444	* by an erratum)
	445	*/
	446	omap3_update_aux_cr(0x2, 0);
	447	}
	448
f1f2c3ca	449	void omap3_outer_cache_disable(void)
45bf0585	450	{
45bf0585	451	/*
cdef0b3f	452	* Clear L2EN
45bf0585 A	453	* On some revisions L2EN bit is banked on some revisions it's not
	454	* No harm in clearing both banked bits(in fact this is required
	455	* by an erratum)
	456	*/
	457	omap3_update_aux_cr(0, 0x2);
	458	}
e3fe6257	459	#endif /* !CONFIG_SYS_L2CACHE_OFF */