[thirdparty/u-boot.git] / arch / arm / mach-orion5x / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
 *
 * Based on original Kirkwood support which is
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 */

#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <u-boot/md5.h>
#include <asm/arch/cpu.h>

#define BUFLEN	16

void reset_cpu(void)
{
	struct orion5x_cpu_registers *cpureg =
	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;

	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
		&cpureg->rstoutn_mask);
	writel(readl(&cpureg->sys_soft_rst) | 1,
		&cpureg->sys_soft_rst);
	while (1)
		;
}

/*
 * Compute Window Size field value from size expressed in bytes
 * Used with the Base register to set the address window size and location.
 * Must be programmed from LSB to MSB as sequence of ones followed by
 * sequence of zeros. The number of ones specifies the size of the window in
 * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
 * NOTES:
 * 1) A sizeval equal to 0x0 specifies 4 GiB.
 * 2) A return value of 0x0 specifies 64 KiB.
 */
unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
{
	/*
	 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
	 * For sizeval > 0 this is equivalent to:
	 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
	 */
	sizeval = (sizeval - 1) >> 16;

	/*
	 * Propagate 'one' bits to the right by 'oring' them.
	 * We need only treat bits 15-0.
	 */
	sizeval |= sizeval >> 1;  /* 'Or' bit 15 onto bit 14 */
	sizeval |= sizeval >> 2;  /* 'Or' bits 15-14 onto bits 13-12 */
	sizeval |= sizeval >> 4;  /* 'Or' bits 15-12 onto bits 11-8 */
	sizeval |= sizeval >> 8;  /* 'Or' bits 15-8 onto bits 7-0*/

	return sizeval;
}

/*
 * orion5x_config_adr_windows - Configure address Windows
 *
 * There are 8 address windows supported by Orion5x Soc to addess different
 * devices. Each window can be configured for size, BAR and remap addr
 * Below configuration is standard for most of the cases
 *
 * If remap function not used, remap_lo must be set as base
 *
 * NOTES:
 *
 * 1) in order to avoid windows with inconsistent control and base values
 *    (which could prevent access to BOOTCS and hence execution from FLASH)
 *    always disable window before writing the base value then reenable it
 *    by writing the control value.
 *
 * 2) in order to avoid losing access to BOOTCS when disabling window 7,
 *    first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
 *    then configure windows 6 for its own target.
 *
 * Reference Documentation:
 * Mbus-L to Mbus Bridge Registers Configuration.
 * (Sec 25.1 and 25.3 of Datasheet)
 */
int orion5x_config_adr_windows(void)
{
	struct orion5x_win_registers *winregs =
		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;

/* Disable window 0, configure it for its intended target, enable it. */
	writel(0, &winregs[0].ctrl);
	writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
	writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
	writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
		ORION5X_WIN_ENABLE), &winregs[0].ctrl);
/* Disable window 1, configure it for its intended target, enable it. */
	writel(0, &winregs[1].ctrl);
	writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
	writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
	writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
		ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
		ORION5X_WIN_ENABLE), &winregs[1].ctrl);
/* Disable window 2, configure it for its intended target, enable it. */
	writel(0, &winregs[2].ctrl);
	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
		ORION5X_WIN_ENABLE), &winregs[2].ctrl);
/* Disable window 3, configure it for its intended target, enable it. */
	writel(0, &winregs[3].ctrl);
	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
		ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
		ORION5X_WIN_ENABLE), &winregs[3].ctrl);
/* Disable window 4, configure it for its intended target, enable it. */
	writel(0, &winregs[4].ctrl);
	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
		ORION5X_WIN_ENABLE), &winregs[4].ctrl);
/* Disable window 5, configure it for its intended target, enable it. */
	writel(0, &winregs[5].ctrl);
	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
		ORION5X_WIN_ENABLE), &winregs[5].ctrl);
/* Disable window 6, configure it for FLASH, enable it. */
	writel(0, &winregs[6].ctrl);
	writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
		ORION5X_WIN_ENABLE), &winregs[6].ctrl);
/* Disable window 7, configure it for FLASH, enable it. */
	writel(0, &winregs[7].ctrl);
	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
		ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
		ORION5X_WIN_ENABLE), &winregs[7].ctrl);
/* Disable window 6, configure it for its intended target, enable it. */
	writel(0, &winregs[6].ctrl);
	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
		ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
		ORION5X_WIN_ENABLE), &winregs[6].ctrl);

	return 0;
}

/*
 * Orion5x identification is done through PCIE space.
 */

u32 orion5x_device_id(void)
{
	return readl(PCIE_DEV_ID_OFF) >> 16;
}

u32 orion5x_device_rev(void)
{
	return readl(PCIE_DEV_REV_OFF) & 0xff;
}

#if defined(CONFIG_DISPLAY_CPUINFO)

/* Display device and revision IDs.
 * This function must cover all known device/revision
 * combinations, not only the one for which u-boot is
 * compiled; this way, one can identify actual HW in
 * case of a mismatch.
 */
int print_cpuinfo(void)
{
	char dev_str[7]; /* room enough for 0x0000 plus null byte */
	char rev_str[5]; /* room enough for 0x00 plus null byte */
	char *dev_name = NULL;
	char *rev_name = NULL;

	u32 dev = orion5x_device_id();
	u32 rev = orion5x_device_rev();

	if (dev == MV88F5181_DEV_ID) {
		dev_name = "MV88F5181";
		if (rev == MV88F5181_REV_B1)
			rev_name = "B1";
		else if (rev == MV88F5181L_REV_A1) {
			dev_name = "MV88F5181L";
			rev_name = "A1";
		} else if (rev == MV88F5181L_REV_A0) {
			dev_name = "MV88F5181L";
			rev_name = "A0";
		}
	} else if (dev == MV88F5182_DEV_ID) {
		dev_name = "MV88F5182";
		if (rev == MV88F5182_REV_A2)
			rev_name = "A2";
	} else if (dev == MV88F5281_DEV_ID) {
		dev_name = "MV88F5281";
		if (rev == MV88F5281_REV_D2)
			rev_name = "D2";
		else if (rev == MV88F5281_REV_D1)
			rev_name = "D1";
		else if (rev == MV88F5281_REV_D0)
			rev_name = "D0";
	} else if (dev == MV88F6183_DEV_ID) {
		dev_name = "MV88F6183";
		if (rev == MV88F6183_REV_B0)
			rev_name = "B0";
	}
	if (dev_name == NULL) {
		sprintf(dev_str, "0x%04x", dev);
		dev_name = dev_str;
	}
	if (rev_name == NULL) {
		sprintf(rev_str, "0x%02x", rev);
		rev_name = rev_str;
	}

	printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);

	return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */

#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
	/* Enable and invalidate L2 cache in write through mode */
	invalidate_l2_cache();

#ifdef CONFIG_SPL_BUILD
	orion5x_config_adr_windows();
#endif

	return 0;
}
#endif /* CONFIG_ARCH_CPU_INIT */

/*
 * SOC specific misc init
 */
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
	u32 temp;

	/*CPU streaming & write allocate */
	temp = readfr_extra_feature_reg();
	temp &= ~(1 << 28);	/* disable wr alloc */
	writefr_extra_feature_reg(temp);

	temp = readfr_extra_feature_reg();
	temp &= ~(1 << 29);	/* streaming disabled */
	writefr_extra_feature_reg(temp);

	/* L2Cache settings */
	temp = readfr_extra_feature_reg();
	/* Disable L2C pre fetch - Set bit 24 */
	temp |= (1 << 24);
	/* enable L2C - Set bit 22 */
	temp |= (1 << 22);
	writefr_extra_feature_reg(temp);

	icache_enable();
	/* Change reset vector to address 0x0 */
	temp = get_cr();
	set_cr(temp & ~CR_V);

	/* Set CPIOs and MPPs - values provided by board
	   include file */
	writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
	writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
	writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
	writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);

	/* initialize timer */
	timer_init_r();
	return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */

#ifdef CONFIG_MVGBE
int cpu_eth_init(struct bd_info *bis)
{
	mvgbe_initialize(bis);
	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
0c61e6f9	2	/*
57b4bce9	3	* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
0c61e6f9 AA	4	*
	5	* Based on original Kirkwood support which is
	6	* (C) Copyright 2009
	7	* Marvell Semiconductor <www.marvell.com>
	8	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
0c61e6f9 AA	9	*/
0c61e6f9 AA	10
d678a59d	11	#include <common.h>
9edefc27	12	#include <cpu_func.h>
691d719d	13	#include <init.h>
90526e9f	14	#include <net.h>
0c61e6f9 AA	15	#include <netdev.h>
0c61e6f9 AA	16	#include <asm/cache.h>
5ff8b354	17	#include <asm/io.h>
0c61e6f9	18	#include <u-boot/md5.h>
5ff8b354	19	#include <asm/arch/cpu.h>
0c61e6f9 AA	20
	21	#define BUFLEN 16
	22
35b65dd8	23	void reset_cpu(void)
0c61e6f9 AA	24	{
	25	struct orion5x_cpu_registers *cpureg =
	26	(struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
	27
	28	writel(readl(&cpureg->rstoutn_mask) \| (1 << 2),
	29	&cpureg->rstoutn_mask);
	30	writel(readl(&cpureg->sys_soft_rst) \| 1,
	31	&cpureg->sys_soft_rst);
	32	while (1)
	33	;
	34	}
	35
	36	/*
500f2ff5	37	* Compute Window Size field value from size expressed in bytes
0c61e6f9 AA	38	* Used with the Base register to set the address window size and location.
	39	* Must be programmed from LSB to MSB as sequence of ones followed by
	40	* sequence of zeros. The number of ones specifies the size of the window in
500f2ff5 AA	41	* 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
	42	* NOTES:
	43	* 1) A sizeval equal to 0x0 specifies 4 GiB.
	44	* 2) A return value of 0x0 specifies 64 KiB.
0c61e6f9 AA	45	*/
	46	unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
	47	{
500f2ff5 AA	48	/*
	49	* Calculate the number of 64 KiB blocks needed minus one (rounding up).
	50	* For sizeval > 0 this is equivalent to:
	51	* sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
	52	*/
	53	sizeval = (sizeval - 1) >> 16;
	54
	55	/*
	56	* Propagate 'one' bits to the right by 'oring' them.
	57	* We need only treat bits 15-0.
	58	*/
	59	sizeval \|= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
	60	sizeval \|= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
	61	sizeval \|= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
	62	sizeval \|= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
0c61e6f9	63
500f2ff5	64	return sizeval;
0c61e6f9 AA	65	}
	66
	67	/*
	68	* orion5x_config_adr_windows - Configure address Windows
	69	*
	70	* There are 8 address windows supported by Orion5x Soc to addess different
	71	* devices. Each window can be configured for size, BAR and remap addr
	72	* Below configuration is standard for most of the cases
	73	*
	74	* If remap function not used, remap_lo must be set as base
	75	*
d778a2fb AA	76	* NOTES:
	77	*
	78	* 1) in order to avoid windows with inconsistent control and base values
	79	* (which could prevent access to BOOTCS and hence execution from FLASH)
	80	* always disable window before writing the base value then reenable it
	81	* by writing the control value.
	82	*
	83	* 2) in order to avoid losing access to BOOTCS when disabling window 7,
	84	* first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
	85	* then configure windows 6 for its own target.
	86	*
0c61e6f9 AA	87	* Reference Documentation:
	88	* Mbus-L to Mbus Bridge Registers Configuration.
	89	* (Sec 25.1 and 25.3 of Datasheet)
	90	*/
	91	int orion5x_config_adr_windows(void)
	92	{
	93	struct orion5x_win_registers *winregs =
	94	(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
	95
d778a2fb AA	96	/* Disable window 0, configure it for its intended target, enable it. */
d778a2fb AA	97	writel(0, &winregs[0].ctrl);
4cfa0ab2 AA	98	writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
	99	writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
	100	writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
d778a2fb AA	101	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
	102	ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
	103	ORION5X_WIN_ENABLE), &winregs[0].ctrl);
	104	/* Disable window 1, configure it for its intended target, enable it. */
	105	writel(0, &winregs[1].ctrl);
4cfa0ab2 AA	106	writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
	107	writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
	108	writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
d778a2fb AA	109	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
	110	ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
	111	ORION5X_WIN_ENABLE), &winregs[1].ctrl);
	112	/* Disable window 2, configure it for its intended target, enable it. */
	113	writel(0, &winregs[2].ctrl);
	114	writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
4cfa0ab2	115	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
0c61e6f9 AA	116	ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
0c61e6f9 AA	117	ORION5X_WIN_ENABLE), &winregs[2].ctrl);
d778a2fb AA	118	/* Disable window 3, configure it for its intended target, enable it. */
	119	writel(0, &winregs[3].ctrl);
	120	writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
4cfa0ab2	121	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
0c61e6f9 AA	122	ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
0c61e6f9 AA	123	ORION5X_WIN_ENABLE), &winregs[3].ctrl);
d778a2fb AA	124	/* Disable window 4, configure it for its intended target, enable it. */
	125	writel(0, &winregs[4].ctrl);
	126	writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
4cfa0ab2	127	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
0c61e6f9 AA	128	ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
0c61e6f9 AA	129	ORION5X_WIN_ENABLE), &winregs[4].ctrl);
d778a2fb AA	130	/* Disable window 5, configure it for its intended target, enable it. */
	131	writel(0, &winregs[5].ctrl);
	132	writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
4cfa0ab2	133	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
0c61e6f9 AA	134	ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
0c61e6f9 AA	135	ORION5X_WIN_ENABLE), &winregs[5].ctrl);
d778a2fb AA	136	/* Disable window 6, configure it for FLASH, enable it. */
	137	writel(0, &winregs[6].ctrl);
	138	writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
	139	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
	140	ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
0c61e6f9	141	ORION5X_WIN_ENABLE), &winregs[6].ctrl);
d778a2fb AA	142	/* Disable window 7, configure it for FLASH, enable it. */
	143	writel(0, &winregs[7].ctrl);
	144	writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
4cfa0ab2	145	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
0c61e6f9 AA	146	ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
0c61e6f9 AA	147	ORION5X_WIN_ENABLE), &winregs[7].ctrl);
d778a2fb AA	148	/* Disable window 6, configure it for its intended target, enable it. */
	149	writel(0, &winregs[6].ctrl);
	150	writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
	151	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
	152	ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
	153	ORION5X_WIN_ENABLE), &winregs[6].ctrl);
0c61e6f9 AA	154
	155	return 0;
	156	}
	157
	158	/*
	159	* Orion5x identification is done through PCIE space.
	160	*/
	161
	162	u32 orion5x_device_id(void)
	163	{
	164	return readl(PCIE_DEV_ID_OFF) >> 16;
	165	}
	166
	167	u32 orion5x_device_rev(void)
	168	{
	169	return readl(PCIE_DEV_REV_OFF) & 0xff;
	170	}
	171
	172	#if defined(CONFIG_DISPLAY_CPUINFO)
	173
	174	/* Display device and revision IDs.
	175	* This function must cover all known device/revision
	176	* combinations, not only the one for which u-boot is
	177	* compiled; this way, one can identify actual HW in
	178	* case of a mismatch.
	179	*/
	180	int print_cpuinfo(void)
	181	{
b823fd9b AA	182	char dev_str[7]; /* room enough for 0x0000 plus null byte */
b823fd9b AA	183	char rev_str[5]; /* room enough for 0x00 plus null byte */
0c61e6f9 AA	184	char *dev_name = NULL;
	185	char *rev_name = NULL;
	186
	187	u32 dev = orion5x_device_id();
	188	u32 rev = orion5x_device_rev();
	189
	190	if (dev == MV88F5181_DEV_ID) {
	191	dev_name = "MV88F5181";
	192	if (rev == MV88F5181_REV_B1)
	193	rev_name = "B1";
	194	else if (rev == MV88F5181L_REV_A1) {
	195	dev_name = "MV88F5181L";
	196	rev_name = "A1";
	197	} else if (rev == MV88F5181L_REV_A0) {
	198	dev_name = "MV88F5181L";
	199	rev_name = "A0";
	200	}
	201	} else if (dev == MV88F5182_DEV_ID) {
	202	dev_name = "MV88F5182";
	203	if (rev == MV88F5182_REV_A2)
	204	rev_name = "A2";
	205	} else if (dev == MV88F5281_DEV_ID) {
	206	dev_name = "MV88F5281";
	207	if (rev == MV88F5281_REV_D2)
	208	rev_name = "D2";
	209	else if (rev == MV88F5281_REV_D1)
	210	rev_name = "D1";
	211	else if (rev == MV88F5281_REV_D0)
	212	rev_name = "D0";
	213	} else if (dev == MV88F6183_DEV_ID) {
	214	dev_name = "MV88F6183";
	215	if (rev == MV88F6183_REV_B0)
	216	rev_name = "B0";
	217	}
	218	if (dev_name == NULL) {
	219	sprintf(dev_str, "0x%04x", dev);
	220	dev_name = dev_str;
	221	}
	222	if (rev_name == NULL) {
	223	sprintf(rev_str, "0x%02x", rev);
	224	rev_name = rev_str;
	225	}
	226
	227	printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
	228
	229	return 0;
	230	}
	231	#endif /* CONFIG_DISPLAY_CPUINFO */
	232
	233	#ifdef CONFIG_ARCH_CPU_INIT
	234	int arch_cpu_init(void)
	235	{
	236	/* Enable and invalidate L2 cache in write through mode */
	237	invalidate_l2_cache();
	238
9608e7de	239	#ifdef CONFIG_SPL_BUILD
0c61e6f9	240	orion5x_config_adr_windows();
9608e7de	241	#endif
0c61e6f9 AA	242
	243	return 0;
	244	}
	245	#endif /* CONFIG_ARCH_CPU_INIT */
	246
	247	/*
	248	* SOC specific misc init
	249	*/
	250	#if defined(CONFIG_ARCH_MISC_INIT)
	251	int arch_misc_init(void)
	252	{
	253	u32 temp;
	254
	255	/CPU streaming & write allocate /
	256	temp = readfr_extra_feature_reg();
	257	temp &= ~(1 << 28); /* disable wr alloc */
	258	writefr_extra_feature_reg(temp);
	259
	260	temp = readfr_extra_feature_reg();
	261	temp &= ~(1 << 29); /* streaming disabled */
	262	writefr_extra_feature_reg(temp);
	263
	264	/* L2Cache settings */
	265	temp = readfr_extra_feature_reg();
	266	/* Disable L2C pre fetch - Set bit 24 */
	267	temp \|= (1 << 24);
	268	/* enable L2C - Set bit 22 */
	269	temp \|= (1 << 22);
	270	writefr_extra_feature_reg(temp);
	271
	272	icache_enable();
	273	/* Change reset vector to address 0x0 */
	274	temp = get_cr();
	275	set_cr(temp & ~CR_V);
	276
	277	/* Set CPIOs and MPPs - values provided by board
	278	include file */
23fdf058 AA	279	writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
	280	writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
	281	writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
491f6c2f	282	writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
23fdf058	283	writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
491f6c2f	284	writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
0c61e6f9	285
d778a2fb AA	286	/* initialize timer */
d778a2fb AA	287	timer_init_r();
0c61e6f9 AA	288	return 0;
	289	}
	290	#endif /* CONFIG_ARCH_MISC_INIT */
d3c9ffd0 AA	291
d3c9ffd0 AA	292	#ifdef CONFIG_MVGBE
b75d8dc5	293	int cpu_eth_init(struct bd_info *bis)
d3c9ffd0 AA	294	{
	295	mvgbe_initialize(bis);
	296	return 0;
	297	}
	298	#endif