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rockchip: rk3288: Fix wrong TPL_TEXT_BASE
[u-boot.git] / arch / arm / mach-rockchip / Kconfig
CommitLineData
2444dae5
SG
1if ARCH_ROCKCHIP
2
041cdb5f
HS
3config ROCKCHIP_RK3036
4 bool "Support Rockchip RK3036"
5 select CPU_V7
a381bcf5
KY
6 select SUPPORT_SPL
7 select SPL
451dcf5c
EC
8 imply USB_FUNCTION_ROCKUSB
9 imply CMD_ROCKUSB
041cdb5f
HS
10 help
11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
13 and video codec support. Peripherals include Gigabit Ethernet,
14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
15
daeed1db
KY
16config ROCKCHIP_RK3128
17 bool "Support Rockchip RK3128"
18 select CPU_V7
19 help
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
22 and video codec support. Peripherals include Gigabit Ethernet,
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
24
0a2be69f
HS
25config ROCKCHIP_RK3188
26 bool "Support Rockchip RK3188"
27 select CPU_V7
0680f1b1 28 select SPL_BOARD_INIT if SPL
0a2be69f 29 select SUPPORT_SPL
0a2be69f 30 select SPL
4bbb05bc
PT
31 select SPL_CLK
32 select SPL_PINCTRL
33 select SPL_REGMAP
34 select SPL_SYSCON
35 select SPL_RAM
36 select SPL_DRIVERS_MISC_SUPPORT
4d9253fb 37 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
008a610b 38 select BOARD_LATE_INIT
0a2be69f
HS
39 select ROCKCHIP_BROM_HELPER
40 help
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
43 video interfaces, several memory options and video codec support.
44 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
45 UART, SPI, I2C and PWMs.
168eef7a
KY
46
47config ROCKCHIP_RK322X
48 bool "Support Rockchip RK3228/RK3229"
49 select CPU_V7
50 select SUPPORT_SPL
51 select SPL
52 select ROCKCHIP_BROM_HELPER
53 select DEBUG_UART_BOARD_INIT
54 help
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
57 and video codec support. Peripherals include Gigabit Ethernet,
58 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
0a2be69f 59
2444dae5
SG
60config ROCKCHIP_RK3288
61 bool "Support Rockchip RK3288"
e0f5dbcb 62 select CPU_V7
0680f1b1 63 select SPL_BOARD_INIT if SPL
a381bcf5
KY
64 select SUPPORT_SPL
65 select SPL
c3d098e7
EC
66 imply USB_FUNCTION_ROCKUSB
67 imply CMD_ROCKUSB
2444dae5
SG
68 help
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
71 video interfaces supporting HDMI and eDP, several DDR3 options
72 and video codec support. Peripherals include Gigabit Ethernet,
ef904bf2 73 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
2444dae5 74
849f672b
JT
75if ROCKCHIP_RK3288
76
77config TPL_LDSCRIPT
78 default "arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds"
79
33554fce
JT
80config TPL_TEXT_BASE
81 default 0xff704000
82
849f672b
JT
83endif
84
85a3cfb8
KY
85config ROCKCHIP_RK3328
86 bool "Support Rockchip RK3328"
87 select ARM64
88 help
89 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
90 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
91 video interfaces supporting HDMI and eDP, several DDR3 options
92 and video codec support. Peripherals include Gigabit Ethernet,
93 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
94
37a0c600
AF
95config ROCKCHIP_RK3368
96 bool "Support Rockchip RK3368"
97 select ARM64
5071457e
PT
98 select SUPPORT_SPL
99 select SUPPORT_TPL
4cf4378e
PT
100 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
101 select TPL_NEEDS_SEPARATE_STACK if TPL
5071457e
PT
102 imply SPL_SEPARATE_BSS
103 imply SPL_SERIAL_SUPPORT
104 imply TPL_SERIAL_SUPPORT
5071457e 105 select DEBUG_UART_BOARD_INIT
37a0c600
AF
106 select SYS_NS16550
107 help
9a8f009f
PT
108 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
109 into a big and little cluster with 4 cores each) Cortex-A53 including
110 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
111 (for the little cluster), PowerVR G6110 based graphics, one video
112 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
113 video codec support.
114
115 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
116 I2S, UARTs, SPI, I2C and PWMs.
37a0c600 117
d9d1242b
PT
118if ROCKCHIP_RK3368
119
120config TPL_LDSCRIPT
121 default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
122
5aa49af3
PT
123config TPL_TEXT_BASE
124 default 0xff8c1000
125
126config TPL_MAX_SIZE
127 default 28672
128
129config TPL_STACK
130 default 0xff8cffff
131
d9d1242b
PT
132endif
133
a381bcf5
KY
134config ROCKCHIP_RK3399
135 bool "Support Rockchip RK3399"
136 select ARM64
66e87cc8
KY
137 select SUPPORT_SPL
138 select SPL
139 select SPL_SEPARATE_BSS
c0508e42
PT
140 select SPL_SERIAL_SUPPORT
141 select SPL_DRIVERS_MISC_SUPPORT
7ee16de5 142 select DEBUG_UART_BOARD_INIT
e3067793 143 select BOARD_LATE_INIT
b4d23f76 144 select ROCKCHIP_BROM_HELPER
a381bcf5
KY
145 help
146 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
147 and quad-core Cortex-A53.
148 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
149 video interfaces supporting HDMI and eDP, several DDR3 options
150 and video codec support. Peripherals include Gigabit Ethernet,
151 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
152
2c1e11dd
AY
153config ROCKCHIP_RV1108
154 bool "Support Rockchip RV1108"
155 select CPU_V7
156 help
157 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
158 and a DSP.
159
ee14d29d 160config SPL_ROCKCHIP_BACK_TO_BROM
b47ea792
XZ
161 bool "SPL returns to bootrom"
162 default y if ROCKCHIP_RK3036
1d845947 163 select ROCKCHIP_BROM_HELPER
ee14d29d
PT
164 depends on SPL
165 help
166 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
167 SPL will return to the boot rom, which will then load the U-Boot
168 binary to keep going on.
169
170config TPL_ROCKCHIP_BACK_TO_BROM
171 bool "TPL returns to bootrom"
172 default y if ROCKCHIP_RK3368
173 select ROCKCHIP_BROM_HELPER
174 depends on TPL
b47ea792
XZ
175 help
176 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
177 SPL will return to the boot rom, which will then load the U-Boot
178 binary to keep going on.
179
e3067793
AY
180config ROCKCHIP_BOOT_MODE_REG
181 hex "Rockchip boot mode flag register address"
182 default 0x200081c8 if ROCKCHIP_RK3036
183 default 0x20004040 if ROCKCHIP_RK3188
184 default 0x110005c8 if ROCKCHIP_RK322X
185 default 0xff730094 if ROCKCHIP_RK3288
186 default 0xff738200 if ROCKCHIP_RK3368
187 default 0xff320300 if ROCKCHIP_RK3399
188 default 0x10300580 if ROCKCHIP_RV1108
189 default 0
190 help
191 The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h)
192 according to the value from this register.
193
fa1392a2
KY
194config ROCKCHIP_SPL_RESERVE_IRAM
195 hex "Size of IRAM reserved in SPL"
8a8106f0 196 default 0
fa1392a2
KY
197 help
198 SPL may need reserve memory for firmware loaded by SPL, whose load
199 address is in IRAM and may overlay with SPL text area if not
200 reserved.
201
1d845947
HS
202config ROCKCHIP_BROM_HELPER
203 bool
204
b377d222
PT
205config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
206 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
207 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
208 help
209 Some Rockchip BROM variants (e.g. on the RK3188) load the
210 first stage in segments and enter multiple times. E.g. on
211 the RK3188, the first 1KB of the first stage are loaded
212 first and entered; after returning to the BROM, the
213 remainder of the first stage is loaded, but the BROM
214 re-enters at the same address/to the same code as previously.
215
216 This enables support code in the BOOT0 hook for the SPL stage
217 to allow multiple entries.
218
219config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
220 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
221 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
222 help
223 Some Rockchip BROM variants (e.g. on the RK3188) load the
224 first stage in segments and enter multiple times. E.g. on
225 the RK3188, the first 1KB of the first stage are loaded
226 first and entered; after returning to the BROM, the
227 remainder of the first stage is loaded, but the BROM
228 re-enters at the same address/to the same code as previously.
229
230 This enables support code in the BOOT0 hook for the TPL stage
231 to allow multiple entries.
232
230e0e09 233config SPL_MMC_SUPPORT
ee14d29d 234 default y if !SPL_ROCKCHIP_BACK_TO_BROM
230e0e09 235
be1d5e03 236source "arch/arm/mach-rockchip/rk3036/Kconfig"
daeed1db 237source "arch/arm/mach-rockchip/rk3128/Kconfig"
0a2be69f 238source "arch/arm/mach-rockchip/rk3188/Kconfig"
b24a8ec1 239source "arch/arm/mach-rockchip/rk322x/Kconfig"
041cdb5f 240source "arch/arm/mach-rockchip/rk3288/Kconfig"
85a3cfb8 241source "arch/arm/mach-rockchip/rk3328/Kconfig"
37a0c600 242source "arch/arm/mach-rockchip/rk3368/Kconfig"
a381bcf5 243source "arch/arm/mach-rockchip/rk3399/Kconfig"
2c1e11dd 244source "arch/arm/mach-rockchip/rv1108/Kconfig"
2444dae5 245endif