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Commit | Line | Data |
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2444dae5 SG |
1 | if ARCH_ROCKCHIP |
2 | ||
041cdb5f HS |
3 | config ROCKCHIP_RK3036 |
4 | bool "Support Rockchip RK3036" | |
5 | select CPU_V7 | |
a381bcf5 KY |
6 | select SUPPORT_SPL |
7 | select SPL | |
041cdb5f HS |
8 | help |
9 | The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 | |
10 | including NEON and GPU, Mali-400 graphics, several DDR3 options | |
11 | and video codec support. Peripherals include Gigabit Ethernet, | |
12 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. | |
13 | ||
0a2be69f HS |
14 | config ROCKCHIP_RK3188 |
15 | bool "Support Rockchip RK3188" | |
16 | select CPU_V7 | |
0680f1b1 | 17 | select SPL_BOARD_INIT if SPL |
0a2be69f | 18 | select SUPPORT_SPL |
0a2be69f | 19 | select SPL |
4bbb05bc PT |
20 | select SPL_CLK |
21 | select SPL_PINCTRL | |
22 | select SPL_REGMAP | |
23 | select SPL_SYSCON | |
24 | select SPL_RAM | |
25 | select SPL_DRIVERS_MISC_SUPPORT | |
4d9253fb | 26 | select SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
008a610b | 27 | select BOARD_LATE_INIT |
0a2be69f HS |
28 | select ROCKCHIP_BROM_HELPER |
29 | help | |
30 | The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 | |
31 | including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two | |
32 | video interfaces, several memory options and video codec support. | |
33 | Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, | |
34 | UART, SPI, I2C and PWMs. | |
168eef7a KY |
35 | |
36 | config ROCKCHIP_RK322X | |
37 | bool "Support Rockchip RK3228/RK3229" | |
38 | select CPU_V7 | |
39 | select SUPPORT_SPL | |
40 | select SPL | |
41 | select ROCKCHIP_BROM_HELPER | |
42 | select DEBUG_UART_BOARD_INIT | |
43 | help | |
44 | The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 | |
45 | including NEON and GPU, Mali-400 graphics, several DDR3 options | |
46 | and video codec support. Peripherals include Gigabit Ethernet, | |
47 | USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. | |
0a2be69f | 48 | |
2444dae5 SG |
49 | config ROCKCHIP_RK3288 |
50 | bool "Support Rockchip RK3288" | |
e0f5dbcb | 51 | select CPU_V7 |
0680f1b1 | 52 | select SPL_BOARD_INIT if SPL |
a381bcf5 KY |
53 | select SUPPORT_SPL |
54 | select SPL | |
2444dae5 SG |
55 | help |
56 | The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 | |
57 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two | |
58 | video interfaces supporting HDMI and eDP, several DDR3 options | |
59 | and video codec support. Peripherals include Gigabit Ethernet, | |
ef904bf2 | 60 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. |
2444dae5 | 61 | |
85a3cfb8 KY |
62 | config ROCKCHIP_RK3328 |
63 | bool "Support Rockchip RK3328" | |
64 | select ARM64 | |
65 | help | |
66 | The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. | |
67 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two | |
68 | video interfaces supporting HDMI and eDP, several DDR3 options | |
69 | and video codec support. Peripherals include Gigabit Ethernet, | |
70 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. | |
71 | ||
37a0c600 AF |
72 | config ROCKCHIP_RK3368 |
73 | bool "Support Rockchip RK3368" | |
74 | select ARM64 | |
5071457e PT |
75 | select SUPPORT_SPL |
76 | select SUPPORT_TPL | |
4cf4378e PT |
77 | select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL |
78 | select TPL_NEEDS_SEPARATE_STACK if TPL | |
5071457e PT |
79 | imply SPL_SEPARATE_BSS |
80 | imply SPL_SERIAL_SUPPORT | |
81 | imply TPL_SERIAL_SUPPORT | |
5071457e | 82 | select DEBUG_UART_BOARD_INIT |
37a0c600 AF |
83 | select SYS_NS16550 |
84 | help | |
9a8f009f PT |
85 | The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised |
86 | into a big and little cluster with 4 cores each) Cortex-A53 including | |
87 | AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache | |
88 | (for the little cluster), PowerVR G6110 based graphics, one video | |
89 | output processor supporting LVDS/HDMI/eDP, several DDR3 options and | |
90 | video codec support. | |
91 | ||
92 | On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, | |
93 | I2S, UARTs, SPI, I2C and PWMs. | |
37a0c600 | 94 | |
d9d1242b PT |
95 | if ROCKCHIP_RK3368 |
96 | ||
97 | config TPL_LDSCRIPT | |
98 | default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" | |
99 | ||
5aa49af3 PT |
100 | config TPL_TEXT_BASE |
101 | default 0xff8c1000 | |
102 | ||
103 | config TPL_MAX_SIZE | |
104 | default 28672 | |
105 | ||
106 | config TPL_STACK | |
107 | default 0xff8cffff | |
108 | ||
d9d1242b PT |
109 | endif |
110 | ||
a381bcf5 KY |
111 | config ROCKCHIP_RK3399 |
112 | bool "Support Rockchip RK3399" | |
113 | select ARM64 | |
66e87cc8 KY |
114 | select SUPPORT_SPL |
115 | select SPL | |
116 | select SPL_SEPARATE_BSS | |
c0508e42 PT |
117 | select SPL_SERIAL_SUPPORT |
118 | select SPL_DRIVERS_MISC_SUPPORT | |
7ee16de5 | 119 | select DEBUG_UART_BOARD_INIT |
a381bcf5 KY |
120 | help |
121 | The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 | |
122 | and quad-core Cortex-A53. | |
123 | including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two | |
124 | video interfaces supporting HDMI and eDP, several DDR3 options | |
125 | and video codec support. Peripherals include Gigabit Ethernet, | |
126 | USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. | |
127 | ||
2c1e11dd AY |
128 | config ROCKCHIP_RV1108 |
129 | bool "Support Rockchip RV1108" | |
130 | select CPU_V7 | |
131 | help | |
132 | The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 | |
133 | and a DSP. | |
134 | ||
ee14d29d | 135 | config SPL_ROCKCHIP_BACK_TO_BROM |
b47ea792 XZ |
136 | bool "SPL returns to bootrom" |
137 | default y if ROCKCHIP_RK3036 | |
1d845947 | 138 | select ROCKCHIP_BROM_HELPER |
ee14d29d PT |
139 | depends on SPL |
140 | help | |
141 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, | |
142 | SPL will return to the boot rom, which will then load the U-Boot | |
143 | binary to keep going on. | |
144 | ||
145 | config TPL_ROCKCHIP_BACK_TO_BROM | |
146 | bool "TPL returns to bootrom" | |
147 | default y if ROCKCHIP_RK3368 | |
148 | select ROCKCHIP_BROM_HELPER | |
149 | depends on TPL | |
b47ea792 XZ |
150 | help |
151 | Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, | |
152 | SPL will return to the boot rom, which will then load the U-Boot | |
153 | binary to keep going on. | |
154 | ||
fa1392a2 KY |
155 | config ROCKCHIP_SPL_RESERVE_IRAM |
156 | hex "Size of IRAM reserved in SPL" | |
157 | default 0x4000 | |
158 | help | |
159 | SPL may need reserve memory for firmware loaded by SPL, whose load | |
160 | address is in IRAM and may overlay with SPL text area if not | |
161 | reserved. | |
162 | ||
1d845947 HS |
163 | config ROCKCHIP_BROM_HELPER |
164 | bool | |
165 | ||
b377d222 PT |
166 | config SPL_ROCKCHIP_EARLYRETURN_TO_BROM |
167 | bool "SPL requires early-return (for RK3188-style BROM) to BROM" | |
168 | depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK | |
169 | help | |
170 | Some Rockchip BROM variants (e.g. on the RK3188) load the | |
171 | first stage in segments and enter multiple times. E.g. on | |
172 | the RK3188, the first 1KB of the first stage are loaded | |
173 | first and entered; after returning to the BROM, the | |
174 | remainder of the first stage is loaded, but the BROM | |
175 | re-enters at the same address/to the same code as previously. | |
176 | ||
177 | This enables support code in the BOOT0 hook for the SPL stage | |
178 | to allow multiple entries. | |
179 | ||
180 | config TPL_ROCKCHIP_EARLYRETURN_TO_BROM | |
181 | bool "TPL requires early-return (for RK3188-style BROM) to BROM" | |
182 | depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK | |
183 | help | |
184 | Some Rockchip BROM variants (e.g. on the RK3188) load the | |
185 | first stage in segments and enter multiple times. E.g. on | |
186 | the RK3188, the first 1KB of the first stage are loaded | |
187 | first and entered; after returning to the BROM, the | |
188 | remainder of the first stage is loaded, but the BROM | |
189 | re-enters at the same address/to the same code as previously. | |
190 | ||
191 | This enables support code in the BOOT0 hook for the TPL stage | |
192 | to allow multiple entries. | |
193 | ||
230e0e09 | 194 | config SPL_MMC_SUPPORT |
ee14d29d | 195 | default y if !SPL_ROCKCHIP_BACK_TO_BROM |
230e0e09 | 196 | |
be1d5e03 | 197 | source "arch/arm/mach-rockchip/rk3036/Kconfig" |
0a2be69f | 198 | source "arch/arm/mach-rockchip/rk3188/Kconfig" |
b24a8ec1 | 199 | source "arch/arm/mach-rockchip/rk322x/Kconfig" |
041cdb5f | 200 | source "arch/arm/mach-rockchip/rk3288/Kconfig" |
85a3cfb8 | 201 | source "arch/arm/mach-rockchip/rk3328/Kconfig" |
37a0c600 | 202 | source "arch/arm/mach-rockchip/rk3368/Kconfig" |
a381bcf5 | 203 | source "arch/arm/mach-rockchip/rk3399/Kconfig" |
2c1e11dd | 204 | source "arch/arm/mach-rockchip/rv1108/Kconfig" |
2444dae5 | 205 | endif |