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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
aa89b554 KY |
2 | /* |
3 | * Copyright (c) 2016 Rockchip Electronics Co., Ltd | |
aa89b554 | 4 | */ |
d678a59d | 5 | #include <common.h> |
09140113 | 6 | #include <command.h> |
88a87bcb | 7 | #include <dm.h> |
9fb625ce | 8 | #include <env.h> |
88a87bcb | 9 | #include <clk.h> |
5255932f | 10 | #include <init.h> |
336d4615 | 11 | #include <malloc.h> |
25c61730 | 12 | #include <asm/armv7.h> |
401d1c4f | 13 | #include <asm/global_data.h> |
8af6cafc | 14 | #include <asm/arch-rockchip/bootrom.h> |
88a87bcb | 15 | #include <asm/arch-rockchip/clock.h> |
eab5c50a | 16 | #include <asm/arch-rockchip/cpu_rk3288.h> |
b52a199e | 17 | #include <asm/arch-rockchip/cru.h> |
15f09a1a | 18 | #include <asm/arch-rockchip/hardware.h> |
070e48b3 | 19 | #include <asm/arch-rockchip/grf_rk3288.h> |
f35c417c | 20 | #include <asm/arch-rockchip/pmu_rk3288.h> |
1e7d2be0 | 21 | #include <asm/arch-rockchip/qos_rk3288.h> |
5d19ddf0 | 22 | #include <asm/arch-rockchip/sdram.h> |
61b29b82 | 23 | #include <linux/err.h> |
f35c417c KY |
24 | |
25 | DECLARE_GLOBAL_DATA_PTR; | |
aa89b554 | 26 | |
070e48b3 | 27 | #define GRF_BASE 0xff770000 |
aa89b554 | 28 | |
8af6cafc | 29 | const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { |
5859bb28 | 30 | [BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000", |
a597a77b | 31 | [BROM_BOOTSOURCE_SPINOR] = "/spi@ff130000/flash@0", |
5859bb28 | 32 | [BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000", |
8af6cafc KY |
33 | }; |
34 | ||
25c61730 KY |
35 | #ifdef CONFIG_SPL_BUILD |
36 | static void configure_l2ctlr(void) | |
37 | { | |
38 | u32 l2ctlr; | |
39 | ||
40 | l2ctlr = read_l2ctlr(); | |
41 | l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ | |
42 | ||
43 | /* | |
44 | * Data RAM write latency: 2 cycles | |
45 | * Data RAM read latency: 2 cycles | |
46 | * Data RAM setup latency: 1 cycle | |
47 | * Tag RAM write latency: 1 cycle | |
48 | * Tag RAM read latency: 1 cycle | |
49 | * Tag RAM setup latency: 1 cycle | |
50 | */ | |
51 | l2ctlr |= (1 << 3 | 1 << 0); | |
52 | write_l2ctlr(l2ctlr); | |
53 | } | |
54 | #endif | |
55 | ||
1e7d2be0 KY |
56 | int rk3288_qos_init(void) |
57 | { | |
58 | int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; | |
59 | /* set vop qos to higher priority */ | |
60 | writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); | |
61 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); | |
62 | ||
63 | if (!fdt_node_check_compatible(gd->fdt_blob, 0, | |
64 | "rockchip,rk3288-tinker")) { | |
65 | /* set isp qos to higher priority */ | |
66 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); | |
67 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); | |
68 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); | |
69 | } | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
aa89b554 KY |
74 | int arch_cpu_init(void) |
75 | { | |
ccab9e7e KY |
76 | #ifdef CONFIG_SPL_BUILD |
77 | configure_l2ctlr(); | |
78 | #else | |
aa89b554 | 79 | /* We do some SoC one time setting here. */ |
070e48b3 | 80 | struct rk3288_grf * const grf = (void *)GRF_BASE; |
aa89b554 KY |
81 | |
82 | /* Use rkpwm by default */ | |
070e48b3 | 83 | rk_setreg(&grf->soc_con2, 1 << 0); |
1e7d2be0 KY |
84 | |
85 | /* | |
86 | * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is | |
87 | * cleared | |
88 | */ | |
89 | rk_clrreg(&grf->soc_con0, 1 << 12); | |
90 | ||
91 | rk3288_qos_init(); | |
ccab9e7e | 92 | #endif |
aa89b554 KY |
93 | |
94 | return 0; | |
95 | } | |
e83e885e KY |
96 | |
97 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT | |
98 | void board_debug_uart_init(void) | |
99 | { | |
100 | /* Enable early UART on the RK3288 */ | |
101 | struct rk3288_grf * const grf = (void *)GRF_BASE; | |
102 | ||
103 | rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | | |
104 | GPIO7C6_MASK << GPIO7C6_SHIFT, | |
105 | GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | | |
106 | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); | |
107 | } | |
108 | #endif | |
88a87bcb | 109 | |
271318a6 KY |
110 | __weak int rk3288_board_late_init(void) |
111 | { | |
112 | return 0; | |
113 | } | |
114 | ||
115 | int rk_board_late_init(void) | |
116 | { | |
271318a6 KY |
117 | return rk3288_board_late_init(); |
118 | } | |
119 | ||
eab5c50a JT |
120 | static int ft_rk3288w_setup(void *blob) |
121 | { | |
122 | const char *path; | |
123 | int offs, ret; | |
124 | ||
125 | path = "/clock-controller@ff760000"; | |
126 | offs = fdt_path_offset(blob, path); | |
127 | if (offs < 0) { | |
128 | debug("failed to found fdt path %s\n", path); | |
129 | return offs; | |
130 | } | |
131 | ||
132 | ret = fdt_setprop_string(blob, offs, "compatible", "rockchip,rk3288w-cru"); | |
133 | if (ret) { | |
134 | printf("failed to set rk3288w-cru compatible (ret=%d)\n", ret); | |
135 | return ret; | |
136 | } | |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
24fea3f8 | 141 | int ft_system_setup(void *blob, struct bd_info *bd) |
eab5c50a JT |
142 | { |
143 | if (soc_is_rk3288w()) | |
144 | return ft_rk3288w_setup(blob); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
09140113 SG |
149 | static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc, |
150 | char *const argv[]) | |
88a87bcb KY |
151 | { |
152 | static const struct { | |
153 | char *name; | |
154 | int id; | |
155 | } clks[] = { | |
156 | { "osc", CLK_OSC }, | |
157 | { "apll", CLK_ARM }, | |
158 | { "dpll", CLK_DDR }, | |
159 | { "cpll", CLK_CODEC }, | |
160 | { "gpll", CLK_GENERAL }, | |
161 | #ifdef CONFIG_ROCKCHIP_RK3036 | |
162 | { "mpll", CLK_NEW }, | |
163 | #else | |
164 | { "npll", CLK_NEW }, | |
165 | #endif | |
166 | }; | |
167 | int ret, i; | |
168 | struct udevice *dev; | |
169 | ||
170 | ret = rockchip_get_clk(&dev); | |
171 | if (ret) { | |
172 | printf("clk-uclass not found\n"); | |
173 | return 0; | |
174 | } | |
175 | ||
176 | for (i = 0; i < ARRAY_SIZE(clks); i++) { | |
177 | struct clk clk; | |
178 | ulong rate; | |
179 | ||
180 | clk.id = clks[i].id; | |
181 | ret = clk_request(dev, &clk); | |
182 | if (ret < 0) | |
183 | continue; | |
184 | ||
185 | rate = clk_get_rate(&clk); | |
186 | printf("%s: %lu\n", clks[i].name, rate); | |
88a87bcb KY |
187 | } |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
192 | U_BOOT_CMD( | |
193 | clock, 2, 1, do_clock, | |
194 | "display information about clocks", | |
195 | "" | |
196 | ); |