[people/ms/u-boot.git] / arch / arm / mach-rockchip / rk3288-board-spl.c

/*
 * (C) Copyright 2015 Google, Inc
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
#include <led.h>
#include <malloc.h>
#include <ram.h>
#include <spl.h>
#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/sdram.h>
#include <asm/arch/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <dm/test.h>
#include <dm/util.h>
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>

DECLARE_GLOBAL_DATA_PTR;

u32 spl_boot_device(void)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	const void *blob = gd->fdt_blob;
	struct udevice *dev;
	const char *bootdev;
	int node;
	int ret;

	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
	debug("Boot device %s\n", bootdev);
	if (!bootdev)
		goto fallback;

	node = fdt_path_offset(blob, bootdev);
	if (node < 0) {
		debug("node=%d\n", node);
		goto fallback;
	}
	ret = device_get_global_by_of_offset(node, &dev);
	if (ret) {
		debug("device at node %s/%d not found: %d\n", bootdev, node,
		      ret);
		goto fallback;
	}
	debug("Found device %s\n", dev->name);
	switch (device_get_uclass_id(dev)) {
	case UCLASS_SPI_FLASH:
		return BOOT_DEVICE_SPI;
	case UCLASS_MMC:
		return BOOT_DEVICE_MMC1;
	default:
		debug("Booting from device uclass '%s' not supported\n",
		      dev_get_uclass_name(dev));
	}

fallback:
#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
	return BOOT_DEVICE_SPI;
#endif
	return BOOT_DEVICE_MMC1;
}

u32 spl_boot_mode(const u32 boot_device)
{
	return MMCSD_MODE_RAW;
}

static void configure_l2ctlr(void)
{
	uint32_t l2ctlr;

	l2ctlr = read_l2ctlr();
	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */

	/*
	* Data RAM write latency: 2 cycles
	* Data RAM read latency: 2 cycles
	* Data RAM setup latency: 1 cycle
	* Tag RAM write latency: 1 cycle
	* Tag RAM read latency: 1 cycle
	* Tag RAM setup latency: 1 cycle
	*/
	l2ctlr |= (1 << 3 | 1 << 0);
	write_l2ctlr(l2ctlr);
}

#ifdef CONFIG_SPL_MMC_SUPPORT
static int configure_emmc(struct udevice *pinctrl)
{
#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)

	struct gpio_desc desc;
	int ret;

	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);

	/*
	 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
	 * use the EMMC_PWREN setting.
	 */
	ret = dm_gpio_lookup_name("D9", &desc);
	if (ret) {
		debug("gpio ret=%d\n", ret);
		return ret;
	}
	ret = dm_gpio_request(&desc, "emmc_pwren");
	if (ret) {
		debug("gpio_request ret=%d\n", ret);
		return ret;
	}
	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
	if (ret) {
		debug("gpio dir ret=%d\n", ret);
		return ret;
	}
	ret = dm_gpio_set_value(&desc, 1);
	if (ret) {
		debug("gpio value ret=%d\n", ret);
		return ret;
	}
#endif
	return 0;
}
#endif

#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
	struct udevice *pmic;
	int ret;

	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
	if (ret)
		return ret;

#if defined(CONFIG_SPL_POWER_SUPPORT)
	/* Increase USB input current to 2A */
	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
	if (ret)
		return ret;

	/* Close charger when USB lower then 3.26V */
	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
	if (ret)
		return ret;
#endif

	return 0;
}
#endif

void board_init_f(ulong dummy)
{
	struct udevice *pinctrl;
	struct udevice *dev;
	int ret;

	/* Example code showing how to enable the debug UART on RK3288 */
#include <asm/arch/grf_rk3288.h>
	/* Enable early UART on the RK3288 */
#define GRF_BASE	0xff770000
	struct rk3288_grf * const grf = (void *)GRF_BASE;

	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
		     GPIO7C6_MASK << GPIO7C6_SHIFT,
		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
	/*
	 * Debug UART can be used from here if required:
	 *
	 * debug_uart_init();
	 * printch('a');
	 * printhex8(0x1234);
	 * printascii("string");
	 */
	debug_uart_init();
	debug("\nspl:debug uart enabled in %s\n", __func__);
	ret = spl_early_init();
	if (ret) {
		debug("spl_early_init() failed: %d\n", ret);
		hang();
	}

	rockchip_timer_init();
	configure_l2ctlr();

	ret = rockchip_get_clk(&dev);
	if (ret) {
		debug("CLK init failed: %d\n", ret);
		return;
	}

	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	if (ret) {
		debug("Pinctrl init failed: %d\n", ret);
		return;
	}

#if !defined(CONFIG_SPL_OF_PLATDATA)
	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
		ret = phycore_init();
		if (ret) {
			debug("Failed to set up phycore power settings: %d\n",
			      ret);
			return;
		}
	}
#endif

	debug("\nspl:init dram\n");
	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (ret) {
		debug("DRAM init failed: %d\n", ret);
		return;
	}
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
	back_to_bootrom();
#endif
}

static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
	struct udevice *dev;
	char *led_name;
	int ret;

	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
	if (!led_name)
		return 0;
	ret = led_get_by_label(led_name, &dev);
	if (ret) {
		debug("%s: get=%d\n", __func__, ret);
		return ret;
	}
	ret = led_set_on(dev, 1);
	if (ret)
		return ret;
#endif

	return 0;
}

void spl_board_init(void)
{
	struct udevice *pinctrl;
	int ret;

	ret = setup_led();

	if (ret) {
		debug("LED ret=%d\n", ret);
		hang();
	}

	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	if (ret) {
		debug("%s: Cannot find pinctrl device\n", __func__);
		goto err;
	}

#ifdef CONFIG_SPL_MMC_SUPPORT
	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
	if (ret) {
		debug("%s: Failed to set up SD card\n", __func__);
		goto err;
	}
	ret = configure_emmc(pinctrl);
	if (ret) {
		debug("%s: Failed to set up eMMC\n", __func__);
		goto err;
	}
#endif

	/* Enable debug UART */
	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
	if (ret) {
		debug("%s: Failed to set up console UART\n", __func__);
		goto err;
	}

	preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
	back_to_bootrom();
#endif
	return;
err:
	printf("spl_board_init: Error %d\n", ret);

	/* No way to report error here */
	hang();
}
Commit	Line	Data
2444dae5 SG	1	/*
	2	* (C) Copyright 2015 Google, Inc
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <debug_uart.h>
	9	#include <dm.h>
	10	#include <fdtdec.h>
bafcf2db	11	#include <i2c.h>
2444dae5 SG	12	#include <led.h>
	13	#include <malloc.h>
	14	#include <ram.h>
	15	#include <spl.h>
d9a7dcf5	16	#include <asm/armv7.h>
2444dae5 SG	17	#include <asm/gpio.h>
2444dae5 SG	18	#include <asm/io.h>
aade077e	19	#include <asm/arch/bootrom.h>
2444dae5 SG	20	#include <asm/arch/clock.h>
	21	#include <asm/arch/hardware.h>
	22	#include <asm/arch/periph.h>
	23	#include <asm/arch/sdram.h>
cc2244b8	24	#include <asm/arch/timer.h>
2444dae5 SG	25	#include <dm/pinctrl.h>
	26	#include <dm/root.h>
	27	#include <dm/test.h>
	28	#include <dm/util.h>
	29	#include <power/regulator.h>
bafcf2db	30	#include <power/rk8xx_pmic.h>
2444dae5 SG	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
	34	u32 spl_boot_device(void)
	35	{
6afc4661	36	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
2444dae5 SG	37	const void *blob = gd->fdt_blob;
	38	struct udevice *dev;
	39	const char *bootdev;
	40	int node;
	41	int ret;
	42
	43	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
	44	debug("Boot device %s\n", bootdev);
	45	if (!bootdev)
	46	goto fallback;
	47
	48	node = fdt_path_offset(blob, bootdev);
	49	if (node < 0) {
	50	debug("node=%d\n", node);
	51	goto fallback;
	52	}
	53	ret = device_get_global_by_of_offset(node, &dev);
	54	if (ret) {
	55	debug("device at node %s/%d not found: %d\n", bootdev, node,
	56	ret);
	57	goto fallback;
	58	}
	59	debug("Found device %s\n", dev->name);
	60	switch (device_get_uclass_id(dev)) {
	61	case UCLASS_SPI_FLASH:
	62	return BOOT_DEVICE_SPI;
	63	case UCLASS_MMC:
	64	return BOOT_DEVICE_MMC1;
	65	default:
	66	debug("Booting from device uclass '%s' not supported\n",
	67	dev_get_uclass_name(dev));
	68	}
	69
	70	fallback:
e70408c0	71	#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) \|\| \
c420ef67 SG	72	defined(CONFIG_TARGET_CHROMEBIT_MICKEY) \|\| \
c420ef67 SG	73	defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
c8816d14	74	return BOOT_DEVICE_SPI;
6afc4661	75	#endif
2444dae5 SG	76	return BOOT_DEVICE_MMC1;
	77	}
	78
2b1cdafa	79	u32 spl_boot_mode(const u32 boot_device)
2444dae5 SG	80	{
	81	return MMCSD_MODE_RAW;
	82	}
	83
2444dae5 SG	84	static void configure_l2ctlr(void)
	85	{
	86	uint32_t l2ctlr;
	87
	88	l2ctlr = read_l2ctlr();
	89	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
	90
	91	/*
	92	* Data RAM write latency: 2 cycles
	93	* Data RAM read latency: 2 cycles
	94	* Data RAM setup latency: 1 cycle
	95	* Tag RAM write latency: 1 cycle
	96	* Tag RAM read latency: 1 cycle
	97	* Tag RAM setup latency: 1 cycle
	98	*/
	99	l2ctlr \|= (1 << 3 \| 1 << 0);
	100	write_l2ctlr(l2ctlr);
	101	}
	102
f23cf909	103	#ifdef CONFIG_SPL_MMC_SUPPORT
2444dae5 SG	104	static int configure_emmc(struct udevice *pinctrl)
2444dae5 SG	105	{
d7ca67b7	106	#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
5051a77b	107
2444dae5 SG	108	struct gpio_desc desc;
	109	int ret;
	110
	111	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
	112
	113	/*
	114	* TODO(sjg@chromium.org): Pick this up from device tree or perhaps
	115	* use the EMMC_PWREN setting.
	116	*/
	117	ret = dm_gpio_lookup_name("D9", &desc);
	118	if (ret) {
	119	debug("gpio ret=%d\n", ret);
	120	return ret;
	121	}
	122	ret = dm_gpio_request(&desc, "emmc_pwren");
	123	if (ret) {
	124	debug("gpio_request ret=%d\n", ret);
	125	return ret;
	126	}
	127	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
	128	if (ret) {
	129	debug("gpio dir ret=%d\n", ret);
	130	return ret;
	131	}
	132	ret = dm_gpio_set_value(&desc, 1);
	133	if (ret) {
	134	debug("gpio value ret=%d\n", ret);
	135	return ret;
	136	}
5051a77b	137	#endif
2444dae5 SG	138	return 0;
2444dae5 SG	139	}
f23cf909	140	#endif
aade077e	141
bafcf2db WE	142	#if !defined(CONFIG_SPL_OF_PLATDATA)
	143	static int phycore_init(void)
	144	{
	145	struct udevice *pmic;
	146	int ret;
	147
	148	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
	149	if (ret)
	150	return ret;
	151
	152	#if defined(CONFIG_SPL_POWER_SUPPORT)
	153	/* Increase USB input current to 2A */
	154	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
	155	if (ret)
	156	return ret;
	157
	158	/* Close charger when USB lower then 3.26V */
	159	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
	160	if (ret)
	161	return ret;
	162	#endif
	163
	164	return 0;
	165	}
	166	#endif
	167
2444dae5 SG	168	void board_init_f(ulong dummy)
	169	{
	170	struct udevice *pinctrl;
	171	struct udevice *dev;
	172	int ret;
	173
	174	/* Example code showing how to enable the debug UART on RK3288 */
2444dae5 SG	175	#include <asm/arch/grf_rk3288.h>
	176	/* Enable early UART on the RK3288 */
	177	#define GRF_BASE 0xff770000
	178	struct rk3288_grf * const grf = (void *)GRF_BASE;
	179
	180	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT \|
	181	GPIO7C6_MASK << GPIO7C6_SHIFT,
	182	GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT \|
	183	GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
	184	/*
	185	* Debug UART can be used from here if required:
	186	*
	187	* debug_uart_init();
	188	* printch('a');
	189	* printhex8(0x1234);
	190	* printascii("string");
	191	*/
	192	debug_uart_init();
7474bbe8	193	debug("\nspl:debug uart enabled in %s\n", __func__);
73976056	194	ret = spl_early_init();
2444dae5	195	if (ret) {
73976056	196	debug("spl_early_init() failed: %d\n", ret);
2444dae5 SG	197	hang();
	198	}
	199
cc2244b8	200	rockchip_timer_init();
2444dae5 SG	201	configure_l2ctlr();
2444dae5 SG	202
c3aad6f6	203	ret = rockchip_get_clk(&dev);
2444dae5 SG	204	if (ret) {
	205	debug("CLK init failed: %d\n", ret);
	206	return;
	207	}
	208
	209	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	210	if (ret) {
	211	debug("Pinctrl init failed: %d\n", ret);
	212	return;
	213	}
bafcf2db WE	214
	215	#if !defined(CONFIG_SPL_OF_PLATDATA)
	216	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
	217	ret = phycore_init();
	218	if (ret) {
	219	debug("Failed to set up phycore power settings: %d\n",
	220	ret);
	221	return;
	222	}
	223	}
	224	#endif
	225
7474bbe8	226	debug("\nspl:init dram\n");
2444dae5 SG	227	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	228	if (ret) {
	229	debug("DRAM init failed: %d\n", ret);
	230	return;
	231	}
ee14d29d	232	#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
b47ea792 XZ	233	back_to_bootrom();
b47ea792 XZ	234	#endif
2444dae5 SG	235	}
	236
	237	static int setup_led(void)
	238	{
	239	#ifdef CONFIG_SPL_LED
	240	struct udevice *dev;
	241	char *led_name;
	242	int ret;
	243
	244	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
	245	if (!led_name)
	246	return 0;
	247	ret = led_get_by_label(led_name, &dev);
	248	if (ret) {
	249	debug("%s: get=%d\n", __func__, ret);
	250	return ret;
	251	}
	252	ret = led_set_on(dev, 1);
	253	if (ret)
	254	return ret;
	255	#endif
	256
	257	return 0;
	258	}
	259
	260	void spl_board_init(void)
	261	{
	262	struct udevice *pinctrl;
	263	int ret;
	264
	265	ret = setup_led();
	266
	267	if (ret) {
	268	debug("LED ret=%d\n", ret);
	269	hang();
	270	}
	271
	272	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	273	if (ret) {
	274	debug("%s: Cannot find pinctrl device\n", __func__);
	275	goto err;
	276	}
5051a77b	277
f23cf909	278	#ifdef CONFIG_SPL_MMC_SUPPORT
5051a77b	279	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
	280	if (ret) {
	281	debug("%s: Failed to set up SD card\n", __func__);
	282	goto err;
	283	}
	284	ret = configure_emmc(pinctrl);
	285	if (ret) {
	286	debug("%s: Failed to set up eMMC\n", __func__);
	287	goto err;
2444dae5	288	}
f23cf909	289	#endif
2444dae5 SG	290
	291	/* Enable debug UART */
	292	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
	293	if (ret) {
	294	debug("%s: Failed to set up console UART\n", __func__);
	295	goto err;
	296	}
	297
	298	preloader_console_init();
ee14d29d	299	#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
427351dc SP	300	back_to_bootrom();
427351dc SP	301	#endif
2444dae5 SG	302	return;
	303	err:
	304	printf("spl_board_init: Error %d\n", ret);
	305
	306	/* No way to report error here */
	307	hang();
	308	}