[thirdparty/u-boot.git] / arch / arm / mach-rockchip / rk3588 / rk3588.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2021 Rockchip Electronics Co., Ltd
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 */

#include <common.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3588.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/ioc_rk3588.h>

#define FIREWALL_DDR_BASE		0xfe030000
#define FW_DDR_MST5_REG			0x54
#define FW_DDR_MST13_REG		0x74
#define FW_DDR_MST21_REG		0x94
#define FW_DDR_MST26_REG		0xa8
#define FW_DDR_MST27_REG		0xac
#define FIREWALL_SYSMEM_BASE		0xfe038000
#define FW_SYSM_MST5_REG		0x54
#define FW_SYSM_MST13_REG		0x74
#define FW_SYSM_MST21_REG		0x94
#define FW_SYSM_MST26_REG		0xa8
#define FW_SYSM_MST27_REG		0xac

#define BUS_IOC_GPIO2A_IOMUX_SEL_L	0x40
#define BUS_IOC_GPIO2B_IOMUX_SEL_L	0x48
#define BUS_IOC_GPIO2D_IOMUX_SEL_L	0x58
#define BUS_IOC_GPIO2D_IOMUX_SEL_H	0x5c
#define BUS_IOC_GPIO3A_IOMUX_SEL_L	0x60

#define SYS_GRF_FORCE_JTAG		BIT(14)

/**
 * Boot-device identifiers used by the BROM on RK3588 when device is booted
 * from SPI flash. IOMUX used for SPI flash affect the value used by the BROM
 * and not the type of SPI flash used.
 */
enum {
	BROM_BOOTSOURCE_FSPI_M0 = 3,
	BROM_BOOTSOURCE_FSPI_M1 = 4,
	BROM_BOOTSOURCE_FSPI_M2 = 6,
};

const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
	[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
	[BROM_BOOTSOURCE_FSPI_M0] = "/spi@fe2b0000/flash@0",
	[BROM_BOOTSOURCE_FSPI_M1] = "/spi@fe2b0000/flash@0",
	[BROM_BOOTSOURCE_FSPI_M2] = "/spi@fe2b0000/flash@0",
	[BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",
};

static struct mm_region rk3588_mem_map[] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0xf0000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		.virt = 0xf0000000UL,
		.phys = 0xf0000000UL,
		.size = 0x10000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	},  {
		.virt = 0x900000000,
		.phys = 0x900000000,
		.size = 0x150000000,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	},  {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = rk3588_mem_map;

/* GPIO0B_IOMUX_SEL_H */
enum {
	GPIO0B5_SHIFT		= 4,
	GPIO0B5_MASK		= GENMASK(7, 4),
	GPIO0B5_REFER		= 8,
	GPIO0B5_UART2_TX_M0	= 10,

	GPIO0B6_SHIFT		= 8,
	GPIO0B6_MASK		= GENMASK(11, 8),
	GPIO0B6_REFER		= 8,
	GPIO0B6_UART2_RX_M0	= 10,
};

void board_debug_uart_init(void)
{
	__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
	static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;

	/* Refer to BUS_IOC */
	rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
		     GPIO0B6_MASK | GPIO0B5_MASK,
		     GPIO0B6_REFER << GPIO0B6_SHIFT |
		     GPIO0B5_REFER << GPIO0B5_SHIFT);

	/* UART2_M0 Switch iomux */
	rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
		     GPIO0B6_MASK | GPIO0B5_MASK,
		     GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
		     GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
}

#ifdef CONFIG_SPL_BUILD
void rockchip_stimer_init(void)
{
	/* If Timer already enabled, don't re-init it */
	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);

	if (reg & 0x1)
		return;

	asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
	writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
}
#endif

#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
	static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE;
#endif
	int secure_reg;

	/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
	secure_reg &= 0xffff0000;
	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);

	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
	secure_reg &= 0xffff;
	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
	secure_reg &= 0xffff0000;
	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);

#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
	/* Disable JTAG exposed on SDMMC */
	rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
#endif
#endif

	return 0;
}
#endif
Commit	Line	Data
f5bc9929 JT	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2021 Rockchip Electronics Co., Ltd
	4	* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
	5	*/
	6
d678a59d	7	#include <common.h>
f5bc9929 JT	8	#include <spl.h>
f5bc9929 JT	9	#include <asm/armv8/mmu.h>
e259f39a	10	#include <asm/arch-rockchip/bootrom.h>
5d710738	11	#include <asm/arch-rockchip/grf_rk3588.h>
f5bc9929 JT	12	#include <asm/arch-rockchip/hardware.h>
	13	#include <asm/arch-rockchip/ioc_rk3588.h>
	14
f5bc9929 JT	15	#define FIREWALL_DDR_BASE 0xfe030000
	16	#define FW_DDR_MST5_REG 0x54
	17	#define FW_DDR_MST13_REG 0x74
	18	#define FW_DDR_MST21_REG 0x94
	19	#define FW_DDR_MST26_REG 0xa8
	20	#define FW_DDR_MST27_REG 0xac
	21	#define FIREWALL_SYSMEM_BASE 0xfe038000
	22	#define FW_SYSM_MST5_REG 0x54
	23	#define FW_SYSM_MST13_REG 0x74
	24	#define FW_SYSM_MST21_REG 0x94
	25	#define FW_SYSM_MST26_REG 0xa8
	26	#define FW_SYSM_MST27_REG 0xac
	27
f5bc9929 JT	28	#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
	29	#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
	30	#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
	31	#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
	32	#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
	33
5d710738 QS	34	#define SYS_GRF_FORCE_JTAG BIT(14)
5d710738 QS	35
0d5104cd JK	36	/**
	37	* Boot-device identifiers used by the BROM on RK3588 when device is booted
	38	* from SPI flash. IOMUX used for SPI flash affect the value used by the BROM
	39	* and not the type of SPI flash used.
	40	*/
	41	enum {
	42	BROM_BOOTSOURCE_FSPI_M0 = 3,
	43	BROM_BOOTSOURCE_FSPI_M1 = 4,
	44	BROM_BOOTSOURCE_FSPI_M2 = 6,
	45	};
	46
e259f39a JK	47	const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
e259f39a JK	48	[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
0d5104cd JK	49	[BROM_BOOTSOURCE_FSPI_M0] = "/spi@fe2b0000/flash@0",
	50	[BROM_BOOTSOURCE_FSPI_M1] = "/spi@fe2b0000/flash@0",
	51	[BROM_BOOTSOURCE_FSPI_M2] = "/spi@fe2b0000/flash@0",
e259f39a JK	52	[BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",
	53	};
	54
f5bc9929 JT	55	static struct mm_region rk3588_mem_map[] = {
	56	{
	57	.virt = 0x0UL,
	58	.phys = 0x0UL,
	59	.size = 0xf0000000UL,
	60	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	61	PTE_BLOCK_INNER_SHARE
	62	}, {
	63	.virt = 0xf0000000UL,
	64	.phys = 0xf0000000UL,
	65	.size = 0x10000000UL,
	66	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	67	PTE_BLOCK_NON_SHARE \|
	68	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	69	}, {
	70	.virt = 0x900000000,
	71	.phys = 0x900000000,
	72	.size = 0x150000000,
	73	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	74	PTE_BLOCK_NON_SHARE \|
	75	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	76	}, {
	77	/* List terminator */
	78	0,
	79	}
	80	};
	81
	82	struct mm_region *mem_map = rk3588_mem_map;
	83
	84	/* GPIO0B_IOMUX_SEL_H */
	85	enum {
	86	GPIO0B5_SHIFT = 4,
	87	GPIO0B5_MASK = GENMASK(7, 4),
	88	GPIO0B5_REFER = 8,
	89	GPIO0B5_UART2_TX_M0 = 10,
	90
	91	GPIO0B6_SHIFT = 8,
	92	GPIO0B6_MASK = GENMASK(11, 8),
	93	GPIO0B6_REFER = 8,
	94	GPIO0B6_UART2_RX_M0 = 10,
	95	};
	96
	97	void board_debug_uart_init(void)
	98	{
	99	__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
	100	static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
	101
	102	/* Refer to BUS_IOC */
	103	rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
	104	GPIO0B6_MASK \| GPIO0B5_MASK,
	105	GPIO0B6_REFER << GPIO0B6_SHIFT \|
	106	GPIO0B5_REFER << GPIO0B5_SHIFT);
	107
	108	/* UART2_M0 Switch iomux */
	109	rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
	110	GPIO0B6_MASK \| GPIO0B5_MASK,
	111	GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT \|
	112	GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
	113	}
	114
	115	#ifdef CONFIG_SPL_BUILD
	116	void rockchip_stimer_init(void)
	117	{
	118	/* If Timer already enabled, don't re-init it */
119	u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
120
121	if (reg & 0x1)
122	return;
123
124	asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
125	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
126	writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
127	writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
128	}
129	#endif
130
131	#ifndef CONFIG_TPL_BUILD
132	int arch_cpu_init(void)
133	{
134	#ifdef CONFIG_SPL_BUILD
5d710738 QS	135	#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
	136	static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE;
	137	#endif
f5bc9929 JT	138	int secure_reg;
	139
	140	/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
	141	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
	142	secure_reg &= 0xffff;
	143	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
	144	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
	145	secure_reg &= 0xffff;
	146	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
	147	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
	148	secure_reg &= 0xffff;
	149	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
	150	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
	151	secure_reg &= 0xffff;
	152	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
	153	secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
	154	secure_reg &= 0xffff0000;
	155	writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
	156
	157	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
	158	secure_reg &= 0xffff;
	159	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
	160	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
	161	secure_reg &= 0xffff;
	162	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
	163	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
	164	secure_reg &= 0xffff;
	165	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
	166	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
	167	secure_reg &= 0xffff;
	168	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
	169	secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
	170	secure_reg &= 0xffff0000;
	171	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
5d710738 QS	172
	173	#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
	174	/* Disable JTAG exposed on SDMMC */
	175	rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
	176	#endif
f5bc9929 JT	177	#endif
	178
	179	return 0;
	180	}
	181	#endif