projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 386fca68 JLL |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2024 Intel Corporation <www.intel.com> | |
| 4 | * | |
| 5 | */ | |
| 6 | ||
| 7 | #include <clk.h> | |
| 8 | #include <config.h> | |
| 9 | #include <dm.h> | |
| 10 | #include <errno.h> | |
| 11 | #include <log.h> | |
| 12 | #include <malloc.h> | |
| 13 | #include <stdarg.h> | |
| 14 | #include <stdio.h> | |
| 15 | #include <time.h> | |
| 16 | #include <vsprintf.h> | |
| 17 | #include <asm/global_data.h> | |
| 18 | #include <asm/io.h> | |
| d678a59d | 19 | #include <asm/u-boot.h> |
| 386fca68 JLL |
20 | #include <linux/kernel.h> |
| 21 | #include <linux/string.h> | |
| 22 | #include <linux/types.h> | |
| 23 | #include <asm/arch/clock_manager.h> | |
| 24 | #include <asm/arch/system_manager.h> | |
| 25 | #include <dt-bindings/clock/agilex5-clock.h> | |
| 26 | ||
| 27 | DECLARE_GLOBAL_DATA_PTR; | |
| 28 | ||
| 29 | static ulong cm_get_rate_dm(u32 id) | |
| 30 | { | |
| 31 | struct udevice *dev; | |
| 32 | struct clk clk; | |
| 33 | ulong rate; | |
| 34 | int ret; | |
| 35 | ||
| 36 | ret = uclass_get_device_by_driver(UCLASS_CLK, | |
| 37 | DM_DRIVER_GET(socfpga_agilex5_clk), | |
| 38 | &dev); | |
| 39 | if (ret) | |
| 40 | return 0; | |
| 41 | ||
| 42 | clk.id = id; | |
| 43 | ret = clk_request(dev, &clk); | |
| 44 | if (ret < 0) | |
| 45 | return 0; | |
| 46 | ||
| 47 | rate = clk_get_rate(&clk); | |
| 48 | ||
| 49 | if ((rate == (unsigned long)-ENOSYS) || | |
| 50 | (rate == (unsigned long)-ENXIO) || | |
| 51 | (rate == (unsigned long)-EIO)) { | |
| 52 | debug("%s id %u: clk_get_rate err: %ld\n", | |
| 53 | __func__, id, rate); | |
| 54 | return 0; | |
| 55 | } | |
| 56 | ||
| 57 | return rate; | |
| 58 | } | |
| 59 | ||
| 60 | static u32 cm_get_rate_dm_khz(u32 id) | |
| 61 | { | |
| 62 | return cm_get_rate_dm(id) / 1000; | |
| 63 | } | |
| 64 | ||
| 65 | unsigned long cm_get_mpu_clk_hz(void) | |
| 66 | { | |
| 67 | return cm_get_rate_dm(AGILEX5_MPU_CLK); | |
| 68 | } | |
| 69 | ||
| 70 | unsigned int cm_get_l4_sys_free_clk_hz(void) | |
| 71 | { | |
| 72 | return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK); | |
| 73 | } | |
| 74 | ||
| 75 | void cm_print_clock_quick_summary(void) | |
| 76 | { | |
| 77 | printf("MPU %10d kHz\n", | |
| 78 | cm_get_rate_dm_khz(AGILEX5_MPU_CLK)); | |
| 79 | printf("L4 Main %8d kHz\n", | |
| 80 | cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK)); | |
| 81 | printf("L4 sys free %8d kHz\n", | |
| 82 | cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK)); | |
| 83 | printf("L4 MP %8d kHz\n", | |
| 84 | cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK)); | |
| 85 | printf("L4 SP %8d kHz\n", | |
| 86 | cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK)); | |
| 87 | printf("SDMMC %8d kHz\n", | |
| 88 | cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK)); | |
| 89 | } |