projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4765ddb0 LFT |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> | |
| 4 | * | |
| 5 | */ | |
| 6 | ||
| db41d65a | 7 | #include <hang.h> |
| 691d719d | 8 | #include <init.h> |
| f7ae49fc | 9 | #include <log.h> |
| 401d1c4f | 10 | #include <asm/global_data.h> |
| 4765ddb0 | 11 | #include <asm/io.h> |
| d678a59d | 12 | #include <asm/u-boot.h> |
| 4765ddb0 | 13 | #include <asm/utils.h> |
| d678a59d | 14 | #include <common.h> |
| aa529663 | 15 | #include <debug_uart.h> |
| 4765ddb0 LFT |
16 | #include <image.h> |
| 17 | #include <spl.h> | |
| 18 | #include <asm/arch/clock_manager.h> | |
| 8b7962a3 | 19 | #include <asm/arch/firewall.h> |
| 4765ddb0 | 20 | #include <asm/arch/mailbox_s10.h> |
| bb25aca1 | 21 | #include <asm/arch/misc.h> |
| 4765ddb0 | 22 | #include <asm/arch/reset_manager.h> |
| 4765ddb0 LFT |
23 | #include <asm/arch/system_manager.h> |
| 24 | #include <watchdog.h> | |
| 6bf238a4 | 25 | #include <dm/uclass.h> |
| 4765ddb0 LFT |
26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; | |
| 28 | ||
| 4765ddb0 LFT |
29 | void board_init_f(ulong dummy) |
| 30 | { | |
| 31 | const struct cm_config *cm_default_cfg = cm_get_default_config(); | |
| 32 | int ret; | |
| 33 | ||
| bb25aca1 LFT |
34 | ret = spl_early_init(); |
| 35 | if (ret) | |
| 36 | hang(); | |
| 37 | ||
| 38 | socfpga_get_managers_addr(); | |
| 39 | ||
| 4765ddb0 | 40 | /* Ensure watchdog is paused when debugging is happening */ |
| db5741f7 | 41 | writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, |
| 2fd1dc55 | 42 | socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); |
| 4765ddb0 | 43 | |
| 2473e13b | 44 | #ifdef CONFIG_HW_WATCHDOG |
| 4765ddb0 LFT |
45 | /* Enable watchdog before initializing the HW */ |
| 46 | socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); | |
| 47 | socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); | |
| 48 | hw_watchdog_init(); | |
| 49 | #endif | |
| 50 | ||
| 51 | /* ensure all processors are not released prior Linux boot */ | |
| 52 | writeq(0, CPU_RELEASE_ADDR); | |
| 53 | ||
| 54 | socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); | |
| 55 | timer_init(); | |
| 56 | ||
| db3b5e98 | 57 | sysmgr_pinmux_init(); |
| 4765ddb0 LFT |
58 | |
| 59 | /* configuring the HPS clocks */ | |
| 60 | cm_basic_init(cm_default_cfg); | |
| 61 | ||
| 62 | #ifdef CONFIG_DEBUG_UART | |
| 63 | socfpga_per_reset(SOCFPGA_RESET(UART0), 0); | |
| 64 | debug_uart_init(); | |
| 65 | #endif | |
| 4765ddb0 LFT |
66 | |
| 67 | preloader_console_init(); | |
| b3e2d9fc | 68 | print_reset_info(); |
| 4765ddb0 LFT |
69 | cm_print_clock_quick_summary(); |
| 70 | ||
| 8b7962a3 | 71 | firewall_setup(); |
| 4765ddb0 LFT |
72 | |
| 73 | /* disable ocram security at CCU for non secure access */ | |
| 74 | clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), | |
| 75 | CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); | |
| 76 | clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), | |
| 77 | CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); | |
| 78 | ||
| 6bf238a4 LFT |
79 | #if CONFIG_IS_ENABLED(ALTERA_SDRAM) |
| 80 | struct udevice *dev; | |
| 81 | ||
| 82 | ret = uclass_get_device(UCLASS_RAM, 0, &dev); | |
| 83 | if (ret) { | |
| 84 | debug("DRAM init failed: %d\n", ret); | |
| 85 | hang(); | |
| 86 | } | |
| 87 | #endif | |
| 4765ddb0 | 88 | |
| 4765ddb0 LFT |
89 | mbox_init(); |
| 90 | ||
| 91 | #ifdef CONFIG_CADENCE_QSPI | |
| 92 | mbox_qspi_open(); | |
| 93 | #endif | |
| 94 | } |