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73175d04 LFT |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
2fb2e047 | 3 | * Copyright (C) 2016-2021 Intel Corporation <www.intel.com> |
73175d04 LFT |
4 | * |
5 | */ | |
6 | ||
e2ffb1da SCL |
7 | #include <asm/arch/handoff_soc64.h> |
8 | #include <asm/arch/system_manager.h> | |
401d1c4f | 9 | #include <asm/global_data.h> |
73175d04 | 10 | #include <asm/io.h> |
d678a59d | 11 | #include <common.h> |
73175d04 LFT |
12 | |
13 | DECLARE_GLOBAL_DATA_PTR; | |
14 | ||
73175d04 LFT |
15 | /* |
16 | * Configure all the pin muxes | |
17 | */ | |
18 | void sysmgr_pinmux_init(void) | |
19 | { | |
20 | populate_sysmgr_pinmux(); | |
21 | populate_sysmgr_fpgaintf_module(); | |
22 | } | |
23 | ||
24 | /* | |
25 | * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting. | |
26 | * The value is not wrote to SYSMGR.FPGAINTF.MODULE but | |
27 | * CONFIG_SYSMGR_ISWGRP_HANDOFF. | |
28 | */ | |
29 | void populate_sysmgr_fpgaintf_module(void) | |
30 | { | |
31 | u32 handoff_val = 0; | |
32 | ||
33 | /* Enable the signal for those HPS peripherals that use FPGA. */ | |
2fd1dc55 | 34 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) == |
db5741f7 | 35 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 36 | handoff_val |= SYSMGR_FPGAINTF_NAND; |
2fd1dc55 | 37 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) == |
db5741f7 | 38 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 39 | handoff_val |= SYSMGR_FPGAINTF_SDMMC; |
2fd1dc55 | 40 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) == |
db5741f7 | 41 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 42 | handoff_val |= SYSMGR_FPGAINTF_SPIM0; |
2fd1dc55 | 43 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) == |
db5741f7 | 44 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 45 | handoff_val |= SYSMGR_FPGAINTF_SPIM1; |
db5741f7 | 46 | writel(handoff_val, |
2fd1dc55 | 47 | socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2); |
73175d04 LFT |
48 | |
49 | handoff_val = 0; | |
2fd1dc55 | 50 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) == |
db5741f7 | 51 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 52 | handoff_val |= SYSMGR_FPGAINTF_EMAC0; |
2fd1dc55 | 53 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) == |
db5741f7 | 54 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 55 | handoff_val |= SYSMGR_FPGAINTF_EMAC1; |
2fd1dc55 | 56 | if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) == |
db5741f7 | 57 | SYSMGR_FPGAINTF_USEFPGA) |
73175d04 | 58 | handoff_val |= SYSMGR_FPGAINTF_EMAC2; |
db5741f7 | 59 | writel(handoff_val, |
2fd1dc55 | 60 | socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3); |
73175d04 LFT |
61 | } |
62 | ||
63 | /* | |
64 | * Configure all the pin muxes | |
65 | */ | |
66 | void populate_sysmgr_pinmux(void) | |
67 | { | |
e2ffb1da | 68 | u32 len, i; |
2fb2e047 TFC |
69 | u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX); |
70 | u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL); | |
71 | u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA); | |
72 | u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY); | |
e2ffb1da SCL |
73 | |
74 | len = (len_mux > len_ioctl) ? len_mux : len_ioctl; | |
75 | len = (len > len_fpga) ? len : len_fpga; | |
76 | len = (len > len_delay) ? len : len_delay; | |
77 | ||
78 | u32 handoff_table[len]; | |
73175d04 LFT |
79 | |
80 | /* setup the pin sel */ | |
e2ffb1da | 81 | len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN; |
2fb2e047 | 82 | socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len); |
73175d04 | 83 | for (i = 0; i < len; i = i + 2) { |
e2ffb1da SCL |
84 | writel(handoff_table[i + 1], |
85 | handoff_table[i] + | |
86 | (u8 *)socfpga_get_sysmgr_addr() + | |
87 | SYSMGR_SOC64_PINSEL0); | |
73175d04 LFT |
88 | } |
89 | ||
90 | /* setup the pin ctrl */ | |
e2ffb1da | 91 | len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN; |
2fb2e047 | 92 | socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len); |
73175d04 | 93 | for (i = 0; i < len; i = i + 2) { |
e2ffb1da SCL |
94 | writel(handoff_table[i + 1], |
95 | handoff_table[i] + | |
96 | (u8 *)socfpga_get_sysmgr_addr() + | |
97 | SYSMGR_SOC64_IOCTRL0); | |
73175d04 LFT |
98 | } |
99 | ||
100 | /* setup the fpga use */ | |
e2ffb1da | 101 | len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN; |
2fb2e047 | 102 | socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len); |
73175d04 | 103 | for (i = 0; i < len; i = i + 2) { |
e2ffb1da SCL |
104 | writel(handoff_table[i + 1], |
105 | handoff_table[i] + | |
db5741f7 | 106 | (u8 *)socfpga_get_sysmgr_addr() + |
2fd1dc55 | 107 | SYSMGR_SOC64_EMAC0_USEFPGA); |
73175d04 LFT |
108 | } |
109 | ||
110 | /* setup the IO delay */ | |
e2ffb1da | 111 | len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN; |
2fb2e047 | 112 | socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len); |
73175d04 | 113 | for (i = 0; i < len; i = i + 2) { |
e2ffb1da SCL |
114 | writel(handoff_table[i + 1], |
115 | handoff_table[i] + | |
116 | (u8 *)socfpga_get_sysmgr_addr() + | |
117 | SYSMGR_SOC64_IODELAY0); | |
73175d04 LFT |
118 | } |
119 | } |