[thirdparty/u-boot.git] / arch / arm / mach-stm32mp / stm32mp1 / spl.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY LOGC_ARCH

#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <ram.h>
#include <spl.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <mach/tzc.h>
#include <linux/libfdt.h>

u32 spl_boot_device(void)
{
	u32 boot_mode;

	boot_mode = get_bootmode();

	switch (boot_mode) {
	case BOOT_FLASH_SD_1:
	case BOOT_FLASH_EMMC_1:
		return BOOT_DEVICE_MMC1;
	case BOOT_FLASH_SD_2:
	case BOOT_FLASH_EMMC_2:
		return BOOT_DEVICE_MMC2;
	case BOOT_SERIAL_UART_1:
	case BOOT_SERIAL_UART_2:
	case BOOT_SERIAL_UART_3:
	case BOOT_SERIAL_UART_4:
	case BOOT_SERIAL_UART_5:
	case BOOT_SERIAL_UART_6:
	case BOOT_SERIAL_UART_7:
	case BOOT_SERIAL_UART_8:
		return BOOT_DEVICE_UART;
	case BOOT_SERIAL_USB_OTG:
		return BOOT_DEVICE_DFU;
	case BOOT_FLASH_NAND_FMC:
		return BOOT_DEVICE_NAND;
	case BOOT_FLASH_NOR_QSPI:
		return BOOT_DEVICE_SPI;
	case BOOT_FLASH_SPINAND_1:
		return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */
	}

	return BOOT_DEVICE_MMC1;
}

u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
{
	return MMCSD_MODE_RAW;
}

#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
int spl_mmc_boot_partition(const u32 boot_device)
{
	switch (boot_device) {
	case BOOT_DEVICE_MMC1:
		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
	case BOOT_DEVICE_MMC2:
		return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
	default:
		return -EINVAL;
	}
}
#endif

#ifdef CONFIG_SPL_DISPLAY_PRINT
void spl_display_print(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	const char *model;

	/* same code than show_board_info() but not compiled for SPL
	 * see CONFIG_DISPLAY_BOARDINFO & common/board_info.c
	 */
	model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
	if (model)
		log_info("Model: %s\n", model);
}
#endif

__weak int board_early_init_f(void)
{
	return 0;
}

uint32_t stm32mp_get_dram_size(void)
{
	struct ram_info ram;
	struct udevice *dev;
	int ret;

	if (uclass_get_device(UCLASS_RAM, 0, &dev))
		return 0;

	ret = ram_get_info(dev, &ram);
	if (ret)
		return 0;

	return ram.size;
}

static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
{
	fdt_addr_t fdt_mem_size;
	fdt_addr_t fdt_start;
	ofnode node;

	node = ofnode_path("/reserved-memory/optee");
	if (!ofnode_valid(node))
		return 0;

	fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
	*start = fdt_start;
	*size = fdt_mem_size;
	return (fdt_start < 0) ? fdt_start : 0;
}

#define CFG_SHMEM_SIZE			0x200000
#define STM32_TZC_NSID_ALL		0xffff
#define STM32_TZC_FILTER_ALL		3

void stm32_init_tzc_for_optee(void)
{
	const uint32_t dram_size = stm32mp_get_dram_size();
	const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
	uint32_t optee_base, optee_size, tee_shmem_base;
	const uintptr_t tzc = STM32_TZC_BASE;
	int ret;

	if (dram_size == 0)
		panic("Cannot determine DRAM size from devicetree\n");

	ret = optee_get_reserved_memory(&optee_base, &optee_size);
	if (ret < 0 || optee_size <= CFG_SHMEM_SIZE)
		panic("Invalid OPTEE reserved memory in devicetree\n");

	tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;

	const struct tzc_region optee_config[] = {
		{
			.base = STM32_DDR_BASE,
			.top = optee_base - 1,
			.sec_mode = TZC_ATTR_SEC_NONE,
			.nsec_id = STM32_TZC_NSID_ALL,
			.filters_mask = STM32_TZC_FILTER_ALL,
		}, {
			.base = optee_base,
			.top = tee_shmem_base - 1,
			.sec_mode = TZC_ATTR_SEC_RW,
			.nsec_id = 0,
			.filters_mask = STM32_TZC_FILTER_ALL,
		}, {
			.base = tee_shmem_base,
			.top = dram_top,
			.sec_mode = TZC_ATTR_SEC_NONE,
			.nsec_id = STM32_TZC_NSID_ALL,
			.filters_mask = STM32_TZC_FILTER_ALL,
		}, {
			.top = 0,
		}
	};

	flush_dcache_all();

	tzc_configure(tzc, optee_config);
	tzc_dump_config(tzc);

	dcache_disable();
}

void spl_board_prepare_for_optee(void *fdt)
{
	stm32_init_tzc_for_optee();
}

void board_init_f(ulong dummy)
{
	struct udevice *dev;
	int ret;

	arch_cpu_init();
	mach_cpu_init();

	ret = spl_early_init();
	if (ret) {
		log_debug("spl_early_init() failed: %d\n", ret);
		hang();
	}

	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
	if (ret) {
		log_debug("Clock init failed: %d\n", ret);
		hang();
	}

	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
	if (ret) {
		log_debug("Reset init failed: %d\n", ret);
		hang();
	}

	ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
	if (ret) {
		log_debug("%s: Cannot find pinctrl device\n", __func__);
		hang();
	}

	/* enable console uart printing */
	preloader_console_init();

	ret = board_early_init_f();
	if (ret) {
		log_debug("board_early_init_f() failed: %d\n", ret);
		hang();
	}

	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (ret) {
		log_err("DRAM init failed: %d\n", ret);
		hang();
	}

	/*
	 * activate cache on DDR only when DDR is fully initialized
	 * to avoid speculative access and issue in get_ram_size()
	 */
	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
		mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
						CONFIG_DDR_CACHEABLE_SIZE,
						DCACHE_DEFAULT_OPTION);
}

void spl_board_prepare_for_boot(void)
{
	dcache_disable();
}

void spl_board_prepare_for_linux(void)
{
	dcache_disable();
}
Commit	Line	Data
4549e789	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2514c2d0 PD	2	/*
2514c2d0 PD	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
2514c2d0 PD	4	*/
2514c2d0 PD	5
eb653acd PD	6	#define LOG_CATEGORY LOGC_ARCH
eb653acd PD	7
d678a59d	8	#include <common.h>
dc7e5f19	9	#include <cpu_func.h>
2514c2d0	10	#include <dm.h>
db41d65a	11	#include <hang.h>
691d719d	12	#include <init.h>
f7ae49fc	13	#include <log.h>
8533263c	14	#include <ram.h>
2514c2d0	15	#include <spl.h>
90526e9f	16	#include <asm/cache.h>
401d1c4f	17	#include <asm/global_data.h>
11dfd1a3	18	#include <asm/io.h>
006ea189	19	#include <asm/arch/sys_proto.h>
8533263c	20	#include <mach/tzc.h>
006ea189	21	#include <linux/libfdt.h>
2514c2d0 PD	22
	23	u32 spl_boot_device(void)
	24	{
11dfd1a3 PD	25	u32 boot_mode;
11dfd1a3 PD	26
7f63c1e6	27	boot_mode = get_bootmode();
11dfd1a3 PD	28
	29	switch (boot_mode) {
	30	case BOOT_FLASH_SD_1:
	31	case BOOT_FLASH_EMMC_1:
	32	return BOOT_DEVICE_MMC1;
	33	case BOOT_FLASH_SD_2:
	34	case BOOT_FLASH_EMMC_2:
	35	return BOOT_DEVICE_MMC2;
7f63c1e6 PD	36	case BOOT_SERIAL_UART_1:
	37	case BOOT_SERIAL_UART_2:
	38	case BOOT_SERIAL_UART_3:
	39	case BOOT_SERIAL_UART_4:
	40	case BOOT_SERIAL_UART_5:
	41	case BOOT_SERIAL_UART_6:
	42	case BOOT_SERIAL_UART_7:
	43	case BOOT_SERIAL_UART_8:
	44	return BOOT_DEVICE_UART;
	45	case BOOT_SERIAL_USB_OTG:
757c8387	46	return BOOT_DEVICE_DFU;
7f63c1e6 PD	47	case BOOT_FLASH_NAND_FMC:
	48	return BOOT_DEVICE_NAND;
	49	case BOOT_FLASH_NOR_QSPI:
	50	return BOOT_DEVICE_SPI;
b664a745 PD	51	case BOOT_FLASH_SPINAND_1:
b664a745 PD	52	return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */
11dfd1a3 PD	53	}
11dfd1a3 PD	54
2514c2d0 PD	55	return BOOT_DEVICE_MMC1;
	56	}
	57
59073573	58	u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
2514c2d0 PD	59	{
	60	return MMCSD_MODE_RAW;
	61	}
	62
40426d6f	63	#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
c51b7518	64	int spl_mmc_boot_partition(const u32 boot_device)
11dfd1a3 PD	65	{
	66	switch (boot_device) {
	67	case BOOT_DEVICE_MMC1:
	68	return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
	69	case BOOT_DEVICE_MMC2:
	70	return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
	71	default:
	72	return -EINVAL;
	73	}
	74	}
40426d6f	75	#endif
11dfd1a3	76
006ea189 PD	77	#ifdef CONFIG_SPL_DISPLAY_PRINT
	78	void spl_display_print(void)
	79	{
	80	DECLARE_GLOBAL_DATA_PTR;
	81	const char *model;
	82
	83	/* same code than show_board_info() but not compiled for SPL
	84	* see CONFIG_DISPLAY_BOARDINFO & common/board_info.c
	85	*/
	86	model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
	87	if (model)
eb653acd	88	log_info("Model: %s\n", model);
006ea189 PD	89	}
	90	#endif
	91
65e38e81 MV	92	__weak int board_early_init_f(void)
	93	{
	94	return 0;
	95	}
	96
8533263c AG	97	uint32_t stm32mp_get_dram_size(void)
	98	{
	99	struct ram_info ram;
	100	struct udevice *dev;
	101	int ret;
	102
	103	if (uclass_get_device(UCLASS_RAM, 0, &dev))
	104	return 0;
	105
	106	ret = ram_get_info(dev, &ram);
	107	if (ret)
	108	return 0;
	109
	110	return ram.size;
	111	}
	112
	113	static int optee_get_reserved_memory(uint32_t start, uint32_t size)
	114	{
55cd74d6	115	fdt_addr_t fdt_mem_size;
8533263c AG	116	fdt_addr_t fdt_start;
	117	ofnode node;
	118
	119	node = ofnode_path("/reserved-memory/optee");
	120	if (!ofnode_valid(node))
	121	return 0;
	122
	123	fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
	124	*start = fdt_start;
	125	*size = fdt_mem_size;
	126	return (fdt_start < 0) ? fdt_start : 0;
	127	}
	128
	129	#define CFG_SHMEM_SIZE 0x200000
	130	#define STM32_TZC_NSID_ALL 0xffff
	131	#define STM32_TZC_FILTER_ALL 3
	132
	133	void stm32_init_tzc_for_optee(void)
	134	{
	135	const uint32_t dram_size = stm32mp_get_dram_size();
	136	const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
	137	uint32_t optee_base, optee_size, tee_shmem_base;
	138	const uintptr_t tzc = STM32_TZC_BASE;
	139	int ret;
	140
	141	if (dram_size == 0)
	142	panic("Cannot determine DRAM size from devicetree\n");
	143
	144	ret = optee_get_reserved_memory(&optee_base, &optee_size);
	145	if (ret < 0 \|\| optee_size <= CFG_SHMEM_SIZE)
	146	panic("Invalid OPTEE reserved memory in devicetree\n");
	147
	148	tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
	149
	150	const struct tzc_region optee_config[] = {
	151	{
	152	.base = STM32_DDR_BASE,
	153	.top = optee_base - 1,
	154	.sec_mode = TZC_ATTR_SEC_NONE,
	155	.nsec_id = STM32_TZC_NSID_ALL,
	156	.filters_mask = STM32_TZC_FILTER_ALL,
	157	}, {
	158	.base = optee_base,
	159	.top = tee_shmem_base - 1,
	160	.sec_mode = TZC_ATTR_SEC_RW,
	161	.nsec_id = 0,
	162	.filters_mask = STM32_TZC_FILTER_ALL,
	163	}, {
	164	.base = tee_shmem_base,
	165	.top = dram_top,
	166	.sec_mode = TZC_ATTR_SEC_NONE,
	167	.nsec_id = STM32_TZC_NSID_ALL,
	168	.filters_mask = STM32_TZC_FILTER_ALL,
	169	}, {
	170	.top = 0,
	171	}
	172	};
	173
	174	flush_dcache_all();
	175
	176	tzc_configure(tzc, optee_config);
	177	tzc_dump_config(tzc);
	178
	179	dcache_disable();
180	}
181
182	void spl_board_prepare_for_optee(void *fdt)
183	{
184	stm32_init_tzc_for_optee();
185	}
186
2514c2d0 PD	187	void board_init_f(ulong dummy)
	188	{
	189	struct udevice *dev;
	190	int ret;
	191
	192	arch_cpu_init();
6df271a7	193	mach_cpu_init();
2514c2d0 PD	194
	195	ret = spl_early_init();
	196	if (ret) {
eb653acd	197	log_debug("spl_early_init() failed: %d\n", ret);
2514c2d0 PD	198	hang();
	199	}
	200
	201	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
	202	if (ret) {
eb653acd	203	log_debug("Clock init failed: %d\n", ret);
eaec1f9e	204	hang();
2514c2d0 PD	205	}
	206
	207	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
	208	if (ret) {
eb653acd	209	log_debug("Reset init failed: %d\n", ret);
eaec1f9e	210	hang();
2514c2d0 PD	211	}
	212
	213	ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
	214	if (ret) {
eb653acd	215	log_debug("%s: Cannot find pinctrl device\n", __func__);
eaec1f9e	216	hang();
2514c2d0 PD	217	}
	218
	219	/* enable console uart printing */
	220	preloader_console_init();
	221
65e38e81 MV	222	ret = board_early_init_f();
65e38e81 MV	223	if (ret) {
eb653acd	224	log_debug("board_early_init_f() failed: %d\n", ret);
65e38e81 MV	225	hang();
	226	}
	227
2514c2d0 PD	228	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
2514c2d0 PD	229	if (ret) {
eb653acd	230	log_err("DRAM init failed: %d\n", ret);
105a5ad6	231	hang();
2514c2d0	232	}
dc7e5f19 PD	233
	234	/*
	235	* activate cache on DDR only when DDR is fully initialized
	236	* to avoid speculative access and issue in get_ram_size()
	237	*/
	238	if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
67f9f11f PD	239	mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
67f9f11f PD	240	CONFIG_DDR_CACHEABLE_SIZE,
dc7e5f19 PD	241	DCACHE_DEFAULT_OPTION);
	242	}
	243
	244	void spl_board_prepare_for_boot(void)
	245	{
	246	dcache_disable();
	247	}
	248
346034a7	249	void spl_board_prepare_for_linux(void)
dc7e5f19 PD	250	{
dc7e5f19 PD	251	dcache_disable();
2514c2d0	252	}