[people/ms/u-boot.git] / arch / arm / mach-sunxi / cpu_info.c

/*
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <axp_pmic.h>
#include <errno.h>

#ifdef CONFIG_MACH_SUN6I
int sunxi_get_ss_bonding_id(void)
{
	struct sunxi_ccm_reg * const ccm =
		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	static int bonding_id = -1;

	if (bonding_id != -1)
		return bonding_id;

	/* Enable Security System */
	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);

	bonding_id = readl(SUNXI_SS_BASE);
	bonding_id = (bonding_id >> 16) & 0x7;

	/* Disable Security System again */
	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);

	return bonding_id;
}
#endif

#ifdef CONFIG_MACH_SUN8I
uint sunxi_get_sram_id(void)
{
	uint id;

	/* Unlock sram info reg, read it, relock */
	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

	return id;
}
#endif

#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
#ifdef CONFIG_MACH_SUN4I
	puts("CPU:   Allwinner A10 (SUN4I)\n");
#elif defined CONFIG_MACH_SUN5I
	u32 val = readl(SUNXI_SID_BASE + 0x08);
	switch ((val >> 12) & 0xf) {
	case 0: puts("CPU:   Allwinner A12 (SUN5I)\n"); break;
	case 3: puts("CPU:   Allwinner A13 (SUN5I)\n"); break;
	case 7: puts("CPU:   Allwinner A10s (SUN5I)\n"); break;
	default: puts("CPU:   Allwinner A1X (SUN5I)\n");
	}
#elif defined CONFIG_MACH_SUN6I
	switch (sunxi_get_ss_bonding_id()) {
	case SUNXI_SS_BOND_ID_A31:
		puts("CPU:   Allwinner A31 (SUN6I)\n");
		break;
	case SUNXI_SS_BOND_ID_A31S:
		puts("CPU:   Allwinner A31s (SUN6I)\n");
		break;
	default:
		printf("CPU:   Allwinner A31? (SUN6I, id: %d)\n",
		       sunxi_get_ss_bonding_id());
	}
#elif defined CONFIG_MACH_SUN7I
	puts("CPU:   Allwinner A20 (SUN7I)\n");
#elif defined CONFIG_MACH_SUN8I_A23
	printf("CPU:   Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_A33
	printf("CPU:   Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_A83T
	printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_H3
	printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_R40
	printf("CPU:   Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_V3S
	printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN9I
	puts("CPU:   Allwinner A80 (SUN9I)\n");
#elif defined CONFIG_MACH_SUN50I
	puts("CPU:   Allwinner A64 (SUN50I)\n");
#elif defined CONFIG_MACH_SUN50I_H5
	puts("CPU:   Allwinner H5 (SUN50I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
	puts("CPU:   SUNXI Family\n");
#endif
	return 0;
}
#endif

#ifdef CONFIG_MACH_SUN8I_H3

#define SIDC_PRCTL 0x40
#define SIDC_RDKEY 0x60

#define SIDC_OP_LOCK 0xAC

uint32_t sun8i_efuse_read(uint32_t offset)
{
	uint32_t reg_val;

	reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL);
	reg_val &= ~(((0x1ff) << 16) | 0x3);
	reg_val |= (offset << 16);
	writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);

	reg_val &= ~(((0xff) << 8) | 0x3);
	reg_val |= (SIDC_OP_LOCK << 8) | 0x2;
	writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);

	while (readl(SUNXI_SIDC_BASE + SIDC_PRCTL) & 0x2);

	reg_val &= ~(((0x1ff) << 16) | ((0xff) << 8) | 0x3);
	writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);

	reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY);
	return reg_val;
}
#endif

int sunxi_get_sid(unsigned int *sid)
{
#ifdef CONFIG_AXP221_POWER
	return axp_get_sid(sid);
#elif defined CONFIG_MACH_SUN8I_H3
	/*
	 * H3 SID controller has a bug, which makes the initial value of
	 * SUNXI_SID_BASE at boot wrong.
	 * Read the value directly from SID controller, in order to get
	 * the correct value, and also refresh the wrong value at
	 * SUNXI_SID_BASE.
	 */
	int i;

	for (i = 0; i< 4; i++)
		sid[i] = sun8i_efuse_read(i * 4);

	return 0;
#elif defined SUNXI_SID_BASE
	int i;

	for (i = 0; i< 4; i++)
		sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);

	return 0;
#else
	return -ENODEV;
#endif
}
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2007-2011
	3	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	4	* Tom Cubie <tangliang@allwinnertech.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/cpu.h>
10191ed0	12	#include <asm/arch/clock.h>
6944aff1	13	#include <axp_pmic.h>
1871a8ca	14	#include <errno.h>
10191ed0 HG	15
	16	#ifdef CONFIG_MACH_SUN6I
	17	int sunxi_get_ss_bonding_id(void)
	18	{
	19	struct sunxi_ccm_reg * const ccm =
	20	(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
	21	static int bonding_id = -1;
	22
	23	if (bonding_id != -1)
	24	return bonding_id;
	25
	26	/* Enable Security System */
	27	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
	28	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
	29
	30	bonding_id = readl(SUNXI_SS_BASE);
	31	bonding_id = (bonding_id >> 16) & 0x7;
	32
	33	/* Disable Security System again */
	34	clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS);
	35	clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS);
	36
	37	return bonding_id;
	38	}
	39	#endif
cba69eee	40
c74384c6 HG	41	#ifdef CONFIG_MACH_SUN8I
	42	uint sunxi_get_sram_id(void)
	43	{
	44	uint id;
	45
	46	/* Unlock sram info reg, read it, relock */
	47	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	48	id = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
	49	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	50
	51	return id;
	52	}
	53	#endif
	54
cba69eee IC	55	#ifdef CONFIG_DISPLAY_CPUINFO
	56	int print_cpuinfo(void)
	57	{
ed41e62f	58	#ifdef CONFIG_MACH_SUN4I
745325a9	59	puts("CPU: Allwinner A10 (SUN4I)\n");
ed41e62f	60	#elif defined CONFIG_MACH_SUN5I
f84269c5 HG	61	u32 val = readl(SUNXI_SID_BASE + 0x08);
	62	switch ((val >> 12) & 0xf) {
	63	case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
	64	case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
	65	case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
	66	default: puts("CPU: Allwinner A1X (SUN5I)\n");
	67	}
ed41e62f	68	#elif defined CONFIG_MACH_SUN6I
10191ed0 HG	69	switch (sunxi_get_ss_bonding_id()) {
	70	case SUNXI_SS_BOND_ID_A31:
	71	puts("CPU: Allwinner A31 (SUN6I)\n");
	72	break;
	73	case SUNXI_SS_BOND_ID_A31S:
	74	puts("CPU: Allwinner A31s (SUN6I)\n");
	75	break;
	76	default:
	77	printf("CPU: Allwinner A31? (SUN6I, id: %d)\n",
	78	sunxi_get_ss_bonding_id());
	79	}
ed41e62f	80	#elif defined CONFIG_MACH_SUN7I
cba69eee	81	puts("CPU: Allwinner A20 (SUN7I)\n");
5e6bacdb	82	#elif defined CONFIG_MACH_SUN8I_A23
c74384c6	83	printf("CPU: Allwinner A23 (SUN8I %04x)\n", sunxi_get_sram_id());
8c3dacff	84	#elif defined CONFIG_MACH_SUN8I_A33
c74384c6 HG	85	printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id());
	86	#elif defined CONFIG_MACH_SUN8I_A83T
	87	printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
1c27b7dc	88	#elif defined CONFIG_MACH_SUN8I_H3
c74384c6	89	printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
379febac CYT	90	#elif defined CONFIG_MACH_SUN8I_R40
379febac CYT	91	printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
c199489f IZ	92	#elif defined CONFIG_MACH_SUN8I_V3S
c199489f IZ	93	printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
1871a8ca HG	94	#elif defined CONFIG_MACH_SUN9I
1871a8ca HG	95	puts("CPU: Allwinner A80 (SUN9I)\n");
d96ebc46 SS	96	#elif defined CONFIG_MACH_SUN50I
d96ebc46 SS	97	puts("CPU: Allwinner A64 (SUN50I)\n");
997bde60 AP	98	#elif defined CONFIG_MACH_SUN50I_H5
997bde60 AP	99	puts("CPU: Allwinner H5 (SUN50I)\n");
745325a9 HG	100	#else
	101	#warning Please update cpu_info.c with correct CPU information
	102	puts("CPU: SUNXI Family\n");
	103	#endif
cba69eee IC	104	return 0;
	105	}
	106	#endif
cac5b1cc	107
65d2d4f2 IZ	108	#ifdef CONFIG_MACH_SUN8I_H3
	109
	110	#define SIDC_PRCTL 0x40
	111	#define SIDC_RDKEY 0x60
	112
	113	#define SIDC_OP_LOCK 0xAC
	114
	115	uint32_t sun8i_efuse_read(uint32_t offset)
	116	{
	117	uint32_t reg_val;
	118
	119	reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL);
	120	reg_val &= ~(((0x1ff) << 16) \| 0x3);
	121	reg_val \|= (offset << 16);
	122	writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
	123
	124	reg_val &= ~(((0xff) << 8) \| 0x3);
	125	reg_val \|= (SIDC_OP_LOCK << 8) \| 0x2;
	126	writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
	127
	128	while (readl(SUNXI_SIDC_BASE + SIDC_PRCTL) & 0x2);
	129
	130	reg_val &= ~(((0x1ff) << 16) \| ((0xff) << 8) \| 0x3);
	131	writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL);
	132
	133	reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY);
	134	return reg_val;
	135	}
	136	#endif
	137
cac5b1cc HG	138	int sunxi_get_sid(unsigned int *sid)
cac5b1cc HG	139	{
cac5b1cc	140	#ifdef CONFIG_AXP221_POWER
6944aff1	141	return axp_get_sid(sid);
65d2d4f2 IZ	142	#elif defined CONFIG_MACH_SUN8I_H3
	143	/*
	144	* H3 SID controller has a bug, which makes the initial value of
	145	* SUNXI_SID_BASE at boot wrong.
	146	* Read the value directly from SID controller, in order to get
	147	* the correct value, and also refresh the wrong value at
	148	* SUNXI_SID_BASE.
	149	*/
	150	int i;
	151
	152	for (i = 0; i< 4; i++)
	153	sid[i] = sun8i_efuse_read(i * 4);
	154
	155	return 0;
813598e3	156	#elif defined SUNXI_SID_BASE
cac5b1cc HG	157	int i;
	158
	159	for (i = 0; i< 4; i++)
0ea5a04f	160	sid[i] = readl((ulong)SUNXI_SID_BASE + 4 * i);
cac5b1cc HG	161
cac5b1cc HG	162	return 0;
813598e3 HG	163	#else
813598e3 HG	164	return -ENODEV;
cac5b1cc HG	165	#endif
cac5b1cc HG	166	}