]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1b245fee | 2 | /* |
f9ec2ec8 | 3 | * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved. |
1b245fee TW |
4 | */ |
5 | ||
d678a59d | 6 | #include <common.h> |
f7ae49fc | 7 | #include <log.h> |
1b245fee TW |
8 | #include <asm/io.h> |
9 | #include <asm/arch/clock.h> | |
10 | #include <asm/arch/gp_padctrl.h> | |
11 | #include <asm/arch/pinmux.h> | |
12 | #include <asm/arch/tegra.h> | |
13 | #include <asm/arch-tegra/clk_rst.h> | |
14 | #include <asm/arch-tegra/pmc.h> | |
15 | #include <asm/arch-tegra/scu.h> | |
c05ed00a | 16 | #include <linux/delay.h> |
1b245fee TW |
17 | #include "cpu.h" |
18 | ||
1b245fee TW |
19 | int get_num_cpus(void) |
20 | { | |
4040ec10 TW |
21 | struct apb_misc_gp_ctlr *gp; |
22 | uint rev; | |
7aaa5a60 | 23 | debug("%s entry\n", __func__); |
4040ec10 TW |
24 | |
25 | gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; | |
26 | rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; | |
27 | ||
28 | switch (rev) { | |
29 | case CHIPID_TEGRA20: | |
30 | return 2; | |
31 | break; | |
32 | case CHIPID_TEGRA30: | |
33 | case CHIPID_TEGRA114: | |
7aaa5a60 TW |
34 | case CHIPID_TEGRA124: |
35 | case CHIPID_TEGRA210: | |
4040ec10 TW |
36 | default: |
37 | return 4; | |
38 | break; | |
39 | } | |
1b245fee TW |
40 | } |
41 | ||
42 | /* | |
43 | * Timing tables for each SOC for all four oscillator options. | |
44 | */ | |
45 | struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { | |
44de8e22 JZ |
46 | /* |
47 | * T20: 1 GHz | |
48 | * | |
49 | * Register Field Bits Width | |
50 | * ------------------------------ | |
51 | * PLLX_BASE p 22:20 3 | |
52 | * PLLX_BASE n 17: 8 10 | |
53 | * PLLX_BASE m 4: 0 5 | |
54 | * PLLX_MISC cpcon 11: 8 4 | |
55 | */ | |
56 | { | |
57 | { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ | |
87a75865 SR |
58 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ |
59 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
60 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
44de8e22 | 61 | { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ |
87a75865 SR |
62 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ |
63 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
64 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
44de8e22 | 65 | { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ |
87a75865 SR |
66 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ |
67 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
68 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
44de8e22 | 69 | { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ |
1b245fee | 70 | }, |
44de8e22 JZ |
71 | /* |
72 | * T25: 1.2 GHz | |
73 | * | |
74 | * Register Field Bits Width | |
75 | * ------------------------------ | |
76 | * PLLX_BASE p 22:20 3 | |
77 | * PLLX_BASE n 17: 8 10 | |
78 | * PLLX_BASE m 4: 0 5 | |
79 | * PLLX_MISC cpcon 11: 8 4 | |
80 | */ | |
81 | { | |
82 | { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */ | |
87a75865 SR |
83 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ |
84 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
85 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
44de8e22 | 86 | { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ |
87a75865 SR |
87 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ |
88 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
89 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
44de8e22 | 90 | { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */ |
87a75865 SR |
91 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ |
92 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
93 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
44de8e22 | 94 | { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */ |
1b245fee | 95 | }, |
44de8e22 | 96 | /* |
2364e151 | 97 | * T30: 600 MHz |
44de8e22 JZ |
98 | * |
99 | * Register Field Bits Width | |
100 | * ------------------------------ | |
101 | * PLLX_BASE p 22:20 3 | |
102 | * PLLX_BASE n 17: 8 10 | |
103 | * PLLX_BASE m 4: 0 5 | |
104 | * PLLX_MISC cpcon 11: 8 4 | |
105 | */ | |
106 | { | |
2364e151 | 107 | { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */ |
87a75865 SR |
108 | { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 16.8 MHz */ |
109 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
110 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
2364e151 | 111 | { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */ |
87a75865 SR |
112 | { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 38.4 MHz */ |
113 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
114 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
2364e151 | 115 | { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */ |
87a75865 SR |
116 | { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 48.0 MHz */ |
117 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
118 | { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */ | |
2364e151 | 119 | { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */ |
1b245fee | 120 | }, |
44de8e22 JZ |
121 | /* |
122 | * T114: 700 MHz | |
123 | * | |
124 | * Register Field Bits Width | |
125 | * ------------------------------ | |
126 | * PLLX_BASE p 23:20 4 | |
127 | * PLLX_BASE n 15: 8 8 | |
128 | * PLLX_BASE m 7: 0 8 | |
129 | */ | |
130 | { | |
131 | { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ | |
87a75865 SR |
132 | { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */ |
133 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
134 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
44de8e22 | 135 | { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ |
87a75865 SR |
136 | { .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */ |
137 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
138 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
44de8e22 | 139 | { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ |
87a75865 SR |
140 | { .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */ |
141 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
142 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
44de8e22 | 143 | { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ |
4040ec10 | 144 | }, |
32edd2ed TW |
145 | |
146 | /* | |
147 | * T124: 700 MHz | |
148 | * | |
149 | * Register Field Bits Width | |
150 | * ------------------------------ | |
151 | * PLLX_BASE p 23:20 4 | |
152 | * PLLX_BASE n 15: 8 8 | |
153 | * PLLX_BASE m 7: 0 8 | |
154 | */ | |
155 | { | |
156 | { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */ | |
87a75865 SR |
157 | { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */ |
158 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
159 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
32edd2ed | 160 | { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */ |
87a75865 SR |
161 | { .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */ |
162 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
163 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
32edd2ed | 164 | { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */ |
87a75865 SR |
165 | { .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */ |
166 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
167 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
32edd2ed TW |
168 | { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */ |
169 | }, | |
7aaa5a60 TW |
170 | |
171 | /* | |
172 | * T210: 700 MHz | |
173 | * | |
174 | * Register Field Bits Width | |
175 | * ------------------------------ | |
176 | * PLLX_BASE p 24:20 5 | |
177 | * PLLX_BASE n 15: 8 8 | |
178 | * PLLX_BASE m 7: 0 8 | |
179 | */ | |
180 | { | |
87a75865 SR |
181 | { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz */ |
182 | { .n = 108, .m = 1, .p = 1 }, /* OSC: 16.0 MHz = 702 MHz */ | |
183 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
184 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
185 | { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz */ | |
3e8650c0 | 186 | { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */ |
87a75865 SR |
187 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ |
188 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
189 | { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz */ | |
3e8650c0 | 190 | { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */ |
87a75865 SR |
191 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ |
192 | { .n = 0, .m = 0, .p = 0 }, /* (N/A) */ | |
193 | { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz */ | |
7aaa5a60 | 194 | }, |
1b245fee TW |
195 | }; |
196 | ||
32edd2ed TW |
197 | static inline void pllx_set_iddq(void) |
198 | { | |
7aaa5a60 | 199 | #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) |
32edd2ed TW |
200 | struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
201 | u32 reg; | |
7aaa5a60 | 202 | debug("%s entry\n", __func__); |
32edd2ed TW |
203 | |
204 | /* Disable IDDQ */ | |
205 | reg = readl(&clkrst->crc_pllx_misc3); | |
206 | reg &= ~PLLX_IDDQ_MASK; | |
207 | writel(reg, &clkrst->crc_pllx_misc3); | |
208 | udelay(2); | |
209 | debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, | |
210 | readl(&clkrst->crc_pllx_misc3)); | |
211 | #endif | |
212 | } | |
213 | ||
1b245fee TW |
214 | int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, |
215 | u32 divp, u32 cpcon) | |
216 | { | |
722e000c | 217 | struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; |
4475c775 | 218 | int chip = tegra_get_chip(); |
1b245fee | 219 | u32 reg; |
7aaa5a60 | 220 | debug("%s entry\n", __func__); |
1b245fee TW |
221 | |
222 | /* If PLLX is already enabled, just return */ | |
223 | if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { | |
7aaa5a60 | 224 | debug("%s: PLLX already enabled, returning\n", __func__); |
1b245fee TW |
225 | return 0; |
226 | } | |
227 | ||
32edd2ed TW |
228 | pllx_set_iddq(); |
229 | ||
1b245fee | 230 | /* Set BYPASS, m, n and p to PLLX_BASE */ |
722e000c TW |
231 | reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); |
232 | reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); | |
1b245fee TW |
233 | writel(reg, &pll->pll_base); |
234 | ||
235 | /* Set cpcon to PLLX_MISC */ | |
4475c775 | 236 | if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30) |
722e000c | 237 | reg = (cpcon << pllinfo->kcp_shift); |
4475c775 TR |
238 | else |
239 | reg = 0; | |
1b245fee | 240 | |
722e000c TW |
241 | /* |
242 | * TODO(twarren@nvidia.com) Check which SoCs use DCCON | |
243 | * and add to pllinfo table if needed! | |
244 | */ | |
245 | /* Set dccon to PLLX_MISC if freq > 600MHz */ | |
1b245fee TW |
246 | if (divn > 600) |
247 | reg |= (1 << PLL_DCCON_SHIFT); | |
248 | writel(reg, &pll->pll_misc); | |
249 | ||
1b245fee | 250 | /* Disable BYPASS */ |
41447fb2 | 251 | reg = readl(&pll->pll_base); |
1b245fee TW |
252 | reg &= ~PLL_BYPASS_MASK; |
253 | writel(reg, &pll->pll_base); | |
7aaa5a60 | 254 | debug("%s: base = 0x%08X\n", __func__, reg); |
1b245fee | 255 | |
722e000c | 256 | /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */ |
1b245fee | 257 | reg = readl(&pll->pll_misc); |
722e000c TW |
258 | if (pllinfo->lock_ena < 32) |
259 | reg |= (1 << pllinfo->lock_ena); | |
1b245fee | 260 | writel(reg, &pll->pll_misc); |
7aaa5a60 | 261 | debug("%s: misc = 0x%08X\n", __func__, reg); |
41447fb2 SW |
262 | |
263 | /* Enable PLLX last, once it's all configured */ | |
264 | reg = readl(&pll->pll_base); | |
265 | reg |= PLL_ENABLE_MASK; | |
266 | writel(reg, &pll->pll_base); | |
7aaa5a60 | 267 | debug("%s: base final = 0x%08X\n", __func__, reg); |
1b245fee TW |
268 | |
269 | return 0; | |
270 | } | |
271 | ||
272 | void init_pllx(void) | |
273 | { | |
274 | struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
275 | struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX]; | |
49493cb7 | 276 | int soc_type, sku_info, chip_sku; |
1b245fee TW |
277 | enum clock_osc_freq osc; |
278 | struct clk_pll_table *sel; | |
7aaa5a60 | 279 | debug("%s entry\n", __func__); |
1b245fee | 280 | |
49493cb7 TW |
281 | /* get SOC (chip) type */ |
282 | soc_type = tegra_get_chip(); | |
7aaa5a60 | 283 | debug("%s: SoC = 0x%02X\n", __func__, soc_type); |
49493cb7 TW |
284 | |
285 | /* get SKU info */ | |
286 | sku_info = tegra_get_sku_info(); | |
7aaa5a60 | 287 | debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info); |
49493cb7 TW |
288 | |
289 | /* get chip SKU, combo of the above info */ | |
290 | chip_sku = tegra_get_chip_sku(); | |
7aaa5a60 | 291 | debug("%s: Chip SKU = %d\n", __func__, chip_sku); |
1b245fee TW |
292 | |
293 | /* get osc freq */ | |
294 | osc = clock_get_osc_freq(); | |
7aaa5a60 | 295 | debug("%s: osc = %d\n", __func__, osc); |
1b245fee TW |
296 | |
297 | /* set pllx */ | |
49493cb7 | 298 | sel = &tegra_pll_x_table[chip_sku][osc]; |
1b245fee | 299 | pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); |
1b245fee TW |
300 | } |
301 | ||
302 | void enable_cpu_clock(int enable) | |
303 | { | |
304 | struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
305 | u32 clk; | |
7aaa5a60 | 306 | debug("%s entry\n", __func__); |
1b245fee TW |
307 | |
308 | /* | |
309 | * NOTE: | |
310 | * Regardless of whether the request is to enable or disable the CPU | |
311 | * clock, every processor in the CPU complex except the master (CPU 0) | |
312 | * will have it's clock stopped because the AVP only talks to the | |
313 | * master. | |
314 | */ | |
315 | ||
316 | if (enable) { | |
317 | /* Initialize PLLX */ | |
318 | init_pllx(); | |
319 | ||
320 | /* Wait until all clocks are stable */ | |
321 | udelay(PLL_STABILIZATION_DELAY); | |
322 | ||
323 | writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol); | |
324 | writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div); | |
325 | } | |
326 | ||
327 | /* | |
328 | * Read the register containing the individual CPU clock enables and | |
329 | * always stop the clocks to CPUs > 0. | |
330 | */ | |
331 | clk = readl(&clkrst->crc_clk_cpu_cmplx); | |
332 | clk |= 1 << CPU1_CLK_STP_SHIFT; | |
4040ec10 TW |
333 | if (get_num_cpus() == 4) |
334 | clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT); | |
335 | ||
1b245fee TW |
336 | /* Stop/Unstop the CPU clock */ |
337 | clk &= ~CPU0_CLK_STP_MASK; | |
338 | clk |= !enable << CPU0_CLK_STP_SHIFT; | |
339 | writel(clk, &clkrst->crc_clk_cpu_cmplx); | |
340 | ||
341 | clock_enable(PERIPH_ID_CPU); | |
342 | } | |
343 | ||
344 | static int is_cpu_powered(void) | |
345 | { | |
f9ec2ec8 TR |
346 | return (tegra_pmc_readl(offsetof(struct pmc_ctlr, |
347 | pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0; | |
1b245fee TW |
348 | } |
349 | ||
350 | static void remove_cpu_io_clamps(void) | |
351 | { | |
1b245fee | 352 | u32 reg; |
7aaa5a60 | 353 | debug("%s entry\n", __func__); |
1b245fee TW |
354 | |
355 | /* Remove the clamps on the CPU I/O signals */ | |
f9ec2ec8 | 356 | reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping)); |
1b245fee | 357 | reg |= CPU_CLMP; |
f9ec2ec8 | 358 | tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping)); |
1b245fee TW |
359 | |
360 | /* Give I/O signals time to stabilize */ | |
361 | udelay(IO_STABILIZATION_DELAY); | |
362 | } | |
363 | ||
364 | void powerup_cpu(void) | |
365 | { | |
1b245fee TW |
366 | u32 reg; |
367 | int timeout = IO_STABILIZATION_DELAY; | |
7aaa5a60 | 368 | debug("%s entry\n", __func__); |
1b245fee TW |
369 | |
370 | if (!is_cpu_powered()) { | |
371 | /* Toggle the CPU power state (OFF -> ON) */ | |
f9ec2ec8 TR |
372 | reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, |
373 | pmc_pwrgate_toggle)); | |
1b245fee TW |
374 | reg &= PARTID_CP; |
375 | reg |= START_CP; | |
f9ec2ec8 TR |
376 | tegra_pmc_writel(reg, |
377 | offsetof(struct pmc_ctlr, | |
378 | pmc_pwrgate_toggle)); | |
1b245fee TW |
379 | |
380 | /* Wait for the power to come up */ | |
381 | while (!is_cpu_powered()) { | |
382 | if (timeout-- == 0) | |
383 | printf("CPU failed to power up!\n"); | |
384 | else | |
385 | udelay(10); | |
386 | } | |
387 | ||
388 | /* | |
389 | * Remove the I/O clamps from CPU power partition. | |
390 | * Recommended only on a Warm boot, if the CPU partition gets | |
391 | * power gated. Shouldn't cause any harm when called after a | |
392 | * cold boot according to HW, probably just redundant. | |
393 | */ | |
394 | remove_cpu_io_clamps(); | |
395 | } | |
396 | } | |
397 | ||
398 | void reset_A9_cpu(int reset) | |
399 | { | |
400 | /* | |
401 | * NOTE: Regardless of whether the request is to hold the CPU in reset | |
402 | * or take it out of reset, every processor in the CPU complex | |
403 | * except the master (CPU 0) will be held in reset because the | |
404 | * AVP only talks to the master. The AVP does not know that there | |
405 | * are multiple processors in the CPU complex. | |
406 | */ | |
407 | int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug; | |
408 | int num_cpus = get_num_cpus(); | |
409 | int cpu; | |
410 | ||
7aaa5a60 | 411 | debug("%s entry\n", __func__); |
1b245fee TW |
412 | /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */ |
413 | for (cpu = 1; cpu < num_cpus; cpu++) | |
414 | reset_cmplx_set_enable(cpu, mask, 1); | |
415 | reset_cmplx_set_enable(0, mask, reset); | |
416 | ||
417 | /* Enable/Disable master CPU reset */ | |
418 | reset_set_enable(PERIPH_ID_CPU, reset); | |
419 | } | |
420 | ||
421 | void clock_enable_coresight(int enable) | |
422 | { | |
4040ec10 | 423 | u32 rst, src = 2; |
1b245fee | 424 | |
7aaa5a60 | 425 | debug("%s entry\n", __func__); |
1b245fee TW |
426 | clock_set_enable(PERIPH_ID_CORESIGHT, enable); |
427 | reset_set_enable(PERIPH_ID_CORESIGHT, !enable); | |
428 | ||
429 | if (enable) { | |
430 | /* | |
49493cb7 | 431 | * Put CoreSight on PLLP_OUT0 and divide it down as per |
32edd2ed | 432 | * PLLP base frequency based on SoC type (T20/T30+). |
49493cb7 TW |
433 | * Clock divider request would setup CSITE clock as 144MHz |
434 | * for PLLP base 216MHz and 204MHz for PLLP base 408MHz | |
1b245fee | 435 | */ |
a4bcd67c | 436 | src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); |
1b245fee TW |
437 | clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src); |
438 | ||
439 | /* Unlock the CPU CoreSight interfaces */ | |
440 | rst = CORESIGHT_UNLOCK; | |
441 | writel(rst, CSITE_CPU_DBG0_LAR); | |
442 | writel(rst, CSITE_CPU_DBG1_LAR); | |
4040ec10 TW |
443 | if (get_num_cpus() == 4) { |
444 | writel(rst, CSITE_CPU_DBG2_LAR); | |
445 | writel(rst, CSITE_CPU_DBG3_LAR); | |
446 | } | |
1b245fee TW |
447 | } |
448 | } | |
449 | ||
450 | void halt_avp(void) | |
451 | { | |
7aaa5a60 TW |
452 | debug("%s entry\n", __func__); |
453 | ||
1b245fee | 454 | for (;;) { |
716ff5ce SW |
455 | writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29), |
456 | FLOW_CTLR_HALT_COP_EVENTS); | |
1b245fee TW |
457 | } |
458 | } |