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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
3f82b1d3 TW |
2 | /* |
3 | * (C) Copyright 2010,2011 | |
4 | * NVIDIA Corporation <www.nvidia.com> | |
3f82b1d3 TW |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
691d719d | 8 | #include <init.h> |
b2871037 | 9 | #include <linux/ctype.h> |
fbcb9256 DS |
10 | #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) |
11 | #include <asm/arch-tegra/pmc.h> | |
3f82b1d3 | 12 | |
fbcb9256 | 13 | static char *get_reset_cause(void) |
b2871037 | 14 | { |
fbcb9256 DS |
15 | struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
16 | ||
17 | switch (pmc->pmc_reset_status) { | |
18 | case 0x00: | |
19 | return "POR"; | |
20 | case 0x01: | |
21 | return "WATCHDOG"; | |
22 | case 0x02: | |
23 | return "SENSOR"; | |
24 | case 0x03: | |
25 | return "SW_MAIN"; | |
26 | case 0x04: | |
27 | return "LP0"; | |
b2871037 | 28 | } |
fbcb9256 | 29 | return "UNKNOWN"; |
b2871037 | 30 | } |
fbcb9256 | 31 | #endif |
b2871037 | 32 | |
3f82b1d3 TW |
33 | /* Print CPU information */ |
34 | int print_cpuinfo(void) | |
35 | { | |
fbcb9256 DS |
36 | printf("SoC: %s\n", CONFIG_SYS_SOC); |
37 | #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30) | |
38 | printf("Reset cause: %s\n", get_reset_cause()); | |
39 | #endif | |
3f82b1d3 TW |
40 | |
41 | /* TBD: Add printf of major/minor rev info, stepping, etc. */ | |
42 | return 0; | |
43 | } |